{"id":816528,"url":"http://patchwork.ozlabs.org/api/patches/816528/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/e1b49cd103c58fba8d74afd1bcbd81441893beb5.1505929556.git.alistair.francis@xilinx.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"","list_archive_url":null,"date":"2017-09-20T22:01:52","name":"[v3,7/8] xlnx-zynqmp-pmu: Connect the IPI device to the PMU","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"a8920163b59504f51ed4b12fa6d13d1398960962","submitter":{"id":47878,"url":"http://patchwork.ozlabs.org/api/people/47878/?format=json","name":"Alistair Francis","email":"alistair.francis@xilinx.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/e1b49cd103c58fba8d74afd1bcbd81441893beb5.1505929556.git.alistair.francis@xilinx.com/mbox/","series":[{"id":4241,"url":"http://patchwork.ozlabs.org/api/series/4241/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=4241","date":"2017-09-20T22:01:31","name":"Add the ZynqMP PMU and IPI","version":3,"mbox":"http://patchwork.ozlabs.org/series/4241/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/816528/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/816528/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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BCL:0; PCL:0;\n\tRULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(100000804101)(100110200095)(100000805101)(100110500095);\n\tSRVR:CY1PR0201MB1932; ","X-Forefront-PRVS":"04362AC73B","SpamDiagnosticOutput":"1:99","SpamDiagnosticMetadata":"NSPM","X-OriginatorOrg":"xilinx.com","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"20 Sep 2017 22:05:39.5030\n\t(UTC)","X-MS-Exchange-CrossTenant-Id":"657af505-d5df-48d0-8300-c31994686c5c","X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp":"TenantId=657af505-d5df-48d0-8300-c31994686c5c; \n\tIp=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01]","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"CY1PR0201MB1932","X-detected-operating-system":"by eggs.gnu.org: Windows 7 or 8 [fuzzy]","X-Received-From":"104.47.37.54","Subject":"[Qemu-devel] [PATCH v3 7/8] xlnx-zynqmp-pmu: Connect the IPI device\n\tto the PMU","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"alistair23@gmail.com, qemu-arm@nongnu.org, alistair.francis@xilinx.com","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"Signed-off-by: Alistair Francis \n---\n\n hw/microblaze/xlnx-zynqmp-pmu.c | 40 ++++++++++++++++++++++++++++++++++------\n 1 file changed, 34 insertions(+), 6 deletions(-)","diff":"diff --git a/hw/microblaze/xlnx-zynqmp-pmu.c b/hw/microblaze/xlnx-zynqmp-pmu.c\nindex ca98d82e87..2016e34db6 100644\n--- a/hw/microblaze/xlnx-zynqmp-pmu.c\n+++ b/hw/microblaze/xlnx-zynqmp-pmu.c\n@@ -24,6 +24,7 @@\n #include \"cpu.h\"\n #include \"boot.h\"\n \n+#include \"hw/intc/xlnx-zynqmp-ipi.h\"\n #include \"hw/intc/xlnx-pmu-iomod-intc.h\"\n \n /* Define the PMU device */\n@@ -38,18 +39,28 @@\n \n #define XLNX_ZYNQMP_PMU_INTC_ADDR 0xFFD40000\n \n+#define XLNX_ZYNQMP_PMU_NUM_IPIS 4\n+static const uint64_t ipi_addr[XLNX_ZYNQMP_PMU_NUM_IPIS] = {\n+ 0xFF340000, 0xFF350000, 0xFF360000, 0xFF370000,\n+};\n+static const uint64_t ipi_irq[XLNX_ZYNQMP_PMU_NUM_IPIS] = {\n+ 19, 20, 21, 22,\n+};\n+\n typedef struct XlnxZynqMPPMUState {\n /*< private >*/\n DeviceState parent_obj;\n \n /*< public >*/\n MicroBlazeCPU cpu;\n+ XlnxZynqMPIPI ipi[XLNX_ZYNQMP_PMU_NUM_IPIS];\n XlnxPMUIOIntc intc;\n } XlnxZynqMPPMUState;\n \n static void xlnx_zynqmp_pmu_init(Object *obj)\n {\n XlnxZynqMPPMUState *s = XLNX_ZYNQMP_PMU(obj);\n+ int i;\n \n object_initialize(&s->cpu, sizeof(s->cpu),\n TYPE_MICROBLAZE_CPU);\n@@ -58,12 +69,19 @@ static void xlnx_zynqmp_pmu_init(Object *obj)\n \n object_initialize(&s->intc, sizeof(s->intc), TYPE_XLNX_PMU_IO_INTC);\n qdev_set_parent_bus(DEVICE(&s->intc), sysbus_get_default());\n+\n+ for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) {\n+ object_initialize(&s->ipi[i], sizeof(s->ipi[i]), TYPE_XLNX_ZYNQMP_IPI);\n+ qdev_set_parent_bus(DEVICE(&s->ipi[i]), sysbus_get_default());\n+ }\n }\n \n static void xlnx_zynqmp_pmu_realize(DeviceState *dev, Error **errp)\n {\n XlnxZynqMPPMUState *s = XLNX_ZYNQMP_PMU(dev);\n Error *err = NULL;\n+ qemu_irq irq[32];\n+ int i;\n \n object_property_set_uint(OBJECT(&s->cpu), XLNX_ZYNQMP_PMU_ROM_ADDR,\n \"base-vectors\", &error_abort);\n@@ -89,12 +107,9 @@ static void xlnx_zynqmp_pmu_realize(DeviceState *dev, Error **errp)\n return;\n }\n \n- object_property_set_uint(OBJECT(&s->intc), 0x10, \"intc-intr-size\",\n- &error_abort);\n- object_property_set_uint(OBJECT(&s->intc), 0x0, \"intc-level-edge\",\n- &error_abort);\n- object_property_set_uint(OBJECT(&s->intc), 0xffff, \"intc-positive\",\n- &error_abort);\n+ object_property_set_uint(OBJECT(&s->intc), 0x10, \"intc-intr-size\", &error_abort);\n+ object_property_set_uint(OBJECT(&s->intc), 0x0, \"intc-level-edge\", &error_abort);\n+ object_property_set_uint(OBJECT(&s->intc), 0xffff, \"intc-positive\", &error_abort);\n object_property_set_bool(OBJECT(&s->intc), true, \"realized\", &err);\n if (err) {\n error_propagate(errp, err);\n@@ -103,6 +118,19 @@ static void xlnx_zynqmp_pmu_realize(DeviceState *dev, Error **errp)\n sysbus_mmio_map(SYS_BUS_DEVICE(&s->intc), 0, XLNX_ZYNQMP_PMU_INTC_ADDR);\n sysbus_connect_irq(SYS_BUS_DEVICE(&s->intc), 0,\n qdev_get_gpio_in(DEVICE(&s->cpu), MB_CPU_IRQ));\n+ for (i = 0; i < 32; i++) {\n+ irq[i] = qdev_get_gpio_in(DEVICE(&s->intc), i);\n+ }\n+\n+ for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) {\n+ object_property_set_bool(OBJECT(&s->ipi[i]), true, \"realized\", &err);\n+ if (err) {\n+ error_propagate(errp, err);\n+ return;\n+ }\n+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi[i]), 0, ipi_addr[i]);\n+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->ipi[i]), 0, irq[ipi_irq[i]]);\n+ }\n }\n \n static void xlnx_zynqmp_pmu_class_init(ObjectClass *oc, void *data)\n","prefixes":["v3","7/8"]}