{"id":816463,"url":"http://patchwork.ozlabs.org/api/patches/816463/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170920201737.25723-5-f4bug@amsat.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170920201737.25723-5-f4bug@amsat.org>","list_archive_url":null,"date":"2017-09-20T20:17:36","name":"[v11,4/5] msf2: Add Smartfusion2 SoC","commit_ref":null,"pull_url":null,"state":"accepted","archived":true,"hash":"6ce5356c78358baae4c351ab7c7b6098b209bd78","submitter":{"id":70924,"url":"http://patchwork.ozlabs.org/api/people/70924/?format=json","name":"Philippe Mathieu-Daudé","email":"f4bug@amsat.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170920201737.25723-5-f4bug@amsat.org/mbox/","series":[{"id":4222,"url":"http://patchwork.ozlabs.org/api/series/4222/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=4222","date":"2017-09-20T20:17:32","name":"Add support for Smartfusion2 SoC","version":11,"mbox":"http://patchwork.ozlabs.org/series/4222/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/816463/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/816463/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400d:c09::241","Subject":"[Qemu-devel] [PATCH v11 4/5] msf2: Add Smartfusion2 SoC","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"From: Subbaraya Sundeep \n\nSmartfusion2 SoC has hardened Microcontroller subsystem\nand flash based FPGA fabric. This patch adds support for\nMicrocontroller subsystem in the SoC.\n\nSigned-off-by: Subbaraya Sundeep \nReviewed-by: Alistair Francis \nSigned-off-by: Philippe Mathieu-Daudé \n[PMD: drop cpu_model to directly use cpu type, check m3clk non null]\n---\n default-configs/arm-softmmu.mak | 1 +\n include/hw/arm/msf2-soc.h | 67 +++++++++++\n hw/arm/msf2-soc.c | 238 ++++++++++++++++++++++++++++++++++++++++\n hw/arm/Makefile.objs | 1 +\n 4 files changed, 307 insertions(+)\n create mode 100644 include/hw/arm/msf2-soc.h\n create mode 100644 hw/arm/msf2-soc.c","diff":"diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak\nindex bbdd3c1d8b..5059d134c8 100644\n--- a/default-configs/arm-softmmu.mak\n+++ b/default-configs/arm-softmmu.mak\n@@ -129,3 +129,4 @@ CONFIG_ACPI=y\n CONFIG_SMBIOS=y\n CONFIG_ASPEED_SOC=y\n CONFIG_GPIO_KEY=y\n+CONFIG_MSF2=y\ndiff --git a/include/hw/arm/msf2-soc.h b/include/hw/arm/msf2-soc.h\nnew file mode 100644\nindex 0000000000..3cfe5c76ee\n--- /dev/null\n+++ b/include/hw/arm/msf2-soc.h\n@@ -0,0 +1,67 @@\n+/*\n+ * Microsemi Smartfusion2 SoC\n+ *\n+ * Copyright (c) 2017 Subbaraya Sundeep \n+ *\n+ * Permission is hereby granted, free of charge, to any person obtaining a copy\n+ * of this software and associated documentation files (the \"Software\"), to deal\n+ * in the Software without restriction, including without limitation the rights\n+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n+ * copies of the Software, and to permit persons to whom the Software is\n+ * furnished to do so, subject to the following conditions:\n+ *\n+ * The above copyright notice and this permission notice shall be included in\n+ * all copies or substantial portions of the Software.\n+ *\n+ * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n+ * THE SOFTWARE.\n+ */\n+\n+#ifndef HW_ARM_MSF2_SOC_H\n+#define HW_ARM_MSF2_SOC_H\n+\n+#include \"hw/arm/armv7m.h\"\n+#include \"hw/timer/mss-timer.h\"\n+#include \"hw/misc/msf2-sysreg.h\"\n+#include \"hw/ssi/mss-spi.h\"\n+\n+#define TYPE_MSF2_SOC \"msf2-soc\"\n+#define MSF2_SOC(obj) OBJECT_CHECK(MSF2State, (obj), TYPE_MSF2_SOC)\n+\n+#define MSF2_NUM_SPIS 2\n+#define MSF2_NUM_UARTS 2\n+\n+/*\n+ * System timer consists of two programmable 32-bit\n+ * decrementing counters that generate individual interrupts to\n+ * the Cortex-M3 processor\n+ */\n+#define MSF2_NUM_TIMERS 2\n+\n+typedef struct MSF2State {\n+ /*< private >*/\n+ SysBusDevice parent_obj;\n+ /*< public >*/\n+\n+ ARMv7MState armv7m;\n+\n+ char *cpu_type;\n+ char *part_name;\n+ uint64_t envm_size;\n+ uint64_t esram_size;\n+\n+ uint32_t m3clk;\n+ uint8_t apb0div;\n+ uint8_t apb1div;\n+\n+ MSF2SysregState sysreg;\n+ MSSTimerState timer;\n+ MSSSpiState spi[MSF2_NUM_SPIS];\n+} MSF2State;\n+\n+#endif\ndiff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c\nnew file mode 100644\nindex 0000000000..6f97fa9fe3\n--- /dev/null\n+++ b/hw/arm/msf2-soc.c\n@@ -0,0 +1,238 @@\n+/*\n+ * SmartFusion2 SoC emulation.\n+ *\n+ * Copyright (c) 2017 Subbaraya Sundeep \n+ *\n+ * Permission is hereby granted, free of charge, to any person obtaining a copy\n+ * of this software and associated documentation files (the \"Software\"), to deal\n+ * in the Software without restriction, including without limitation the rights\n+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n+ * copies of the Software, and to permit persons to whom the Software is\n+ * furnished to do so, subject to the following conditions:\n+ *\n+ * The above copyright notice and this permission notice shall be included in\n+ * all copies or substantial portions of the Software.\n+ *\n+ * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n+ * THE SOFTWARE.\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"qapi/error.h\"\n+#include \"qemu-common.h\"\n+#include \"hw/arm/arm.h\"\n+#include \"exec/address-spaces.h\"\n+#include \"hw/char/serial.h\"\n+#include \"hw/boards.h\"\n+#include \"sysemu/block-backend.h\"\n+#include \"qemu/cutils.h\"\n+#include \"hw/arm/msf2-soc.h\"\n+#include \"hw/misc/unimp.h\"\n+\n+#define MSF2_TIMER_BASE 0x40004000\n+#define MSF2_SYSREG_BASE 0x40038000\n+\n+#define ENVM_BASE_ADDRESS 0x60000000\n+\n+#define SRAM_BASE_ADDRESS 0x20000000\n+\n+#define MSF2_ENVM_MAX_SIZE (512 * K_BYTE)\n+\n+/*\n+ * eSRAM max size is 80k without SECDED(Single error correction and\n+ * dual error detection) feature and 64k with SECDED.\n+ * We do not support SECDED now.\n+ */\n+#define MSF2_ESRAM_MAX_SIZE (80 * K_BYTE)\n+\n+static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 , 0x40011000 };\n+static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 , 0x40010000 };\n+\n+static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 };\n+static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 };\n+static const int timer_irq[MSF2_NUM_TIMERS] = { 14, 15 };\n+\n+static void m2sxxx_soc_initfn(Object *obj)\n+{\n+ MSF2State *s = MSF2_SOC(obj);\n+ int i;\n+\n+ object_initialize(&s->armv7m, sizeof(s->armv7m), TYPE_ARMV7M);\n+ qdev_set_parent_bus(DEVICE(&s->armv7m), sysbus_get_default());\n+\n+ object_initialize(&s->sysreg, sizeof(s->sysreg), TYPE_MSF2_SYSREG);\n+ qdev_set_parent_bus(DEVICE(&s->sysreg), sysbus_get_default());\n+\n+ object_initialize(&s->timer, sizeof(s->timer), TYPE_MSS_TIMER);\n+ qdev_set_parent_bus(DEVICE(&s->timer), sysbus_get_default());\n+\n+ for (i = 0; i < MSF2_NUM_SPIS; i++) {\n+ object_initialize(&s->spi[i], sizeof(s->spi[i]),\n+ TYPE_MSS_SPI);\n+ qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());\n+ }\n+}\n+\n+static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)\n+{\n+ MSF2State *s = MSF2_SOC(dev_soc);\n+ DeviceState *dev, *armv7m;\n+ SysBusDevice *busdev;\n+ Error *err = NULL;\n+ int i;\n+\n+ MemoryRegion *system_memory = get_system_memory();\n+ MemoryRegion *nvm = g_new(MemoryRegion, 1);\n+ MemoryRegion *nvm_alias = g_new(MemoryRegion, 1);\n+ MemoryRegion *sram = g_new(MemoryRegion, 1);\n+\n+ memory_region_init_rom(nvm, NULL, \"MSF2.eNVM\", s->envm_size,\n+ &error_fatal);\n+ /*\n+ * On power-on, the eNVM region 0x60000000 is automatically\n+ * remapped to the Cortex-M3 processor executable region\n+ * start address (0x0). We do not support remapping other eNVM,\n+ * eSRAM and DDR regions by guest(via Sysreg) currently.\n+ */\n+ memory_region_init_alias(nvm_alias, NULL, \"MSF2.eNVM\",\n+ nvm, 0, s->envm_size);\n+\n+ memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, nvm);\n+ memory_region_add_subregion(system_memory, 0, nvm_alias);\n+\n+ memory_region_init_ram(sram, NULL, \"MSF2.eSRAM\", s->esram_size,\n+ &error_fatal);\n+ memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);\n+\n+ armv7m = DEVICE(&s->armv7m);\n+ qdev_prop_set_uint32(armv7m, \"num-irq\", 81);\n+ qdev_prop_set_string(armv7m, \"cpu-type\", s->cpu_type);\n+ object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),\n+ \"memory\", &error_abort);\n+ object_property_set_bool(OBJECT(&s->armv7m), true, \"realized\", &err);\n+ if (err != NULL) {\n+ error_propagate(errp, err);\n+ return;\n+ }\n+\n+ if (!s->m3clk) {\n+ error_setg(errp, \"Invalid m3clk value\");\n+ error_append_hint(errp, \"m3clk can not be zero\\n\");\n+ return;\n+ }\n+ system_clock_scale = NANOSECONDS_PER_SECOND / s->m3clk;\n+\n+ for (i = 0; i < MSF2_NUM_UARTS; i++) {\n+ if (serial_hds[i]) {\n+ serial_mm_init(get_system_memory(), uart_addr[i], 2,\n+ qdev_get_gpio_in(armv7m, uart_irq[i]),\n+ 115200, serial_hds[i], DEVICE_NATIVE_ENDIAN);\n+ }\n+ }\n+\n+ dev = DEVICE(&s->timer);\n+ /* APB0 clock is the timer input clock */\n+ qdev_prop_set_uint32(dev, \"clock-frequency\", s->m3clk / s->apb0div);\n+ object_property_set_bool(OBJECT(&s->timer), true, \"realized\", &err);\n+ if (err != NULL) {\n+ error_propagate(errp, err);\n+ return;\n+ }\n+ busdev = SYS_BUS_DEVICE(dev);\n+ sysbus_mmio_map(busdev, 0, MSF2_TIMER_BASE);\n+ sysbus_connect_irq(busdev, 0,\n+ qdev_get_gpio_in(armv7m, timer_irq[0]));\n+ sysbus_connect_irq(busdev, 1,\n+ qdev_get_gpio_in(armv7m, timer_irq[1]));\n+\n+ dev = DEVICE(&s->sysreg);\n+ qdev_prop_set_uint32(dev, \"apb0divisor\", s->apb0div);\n+ qdev_prop_set_uint32(dev, \"apb1divisor\", s->apb1div);\n+ object_property_set_bool(OBJECT(&s->sysreg), true, \"realized\", &err);\n+ if (err != NULL) {\n+ error_propagate(errp, err);\n+ return;\n+ }\n+ busdev = SYS_BUS_DEVICE(dev);\n+ sysbus_mmio_map(busdev, 0, MSF2_SYSREG_BASE);\n+\n+ for (i = 0; i < MSF2_NUM_SPIS; i++) {\n+ gchar *bus_name;\n+\n+ object_property_set_bool(OBJECT(&s->spi[i]), true, \"realized\", &err);\n+ if (err != NULL) {\n+ error_propagate(errp, err);\n+ return;\n+ }\n+\n+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);\n+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,\n+ qdev_get_gpio_in(armv7m, spi_irq[i]));\n+\n+ /* Alias controller SPI bus to the SoC itself */\n+ bus_name = g_strdup_printf(\"spi%d\", i);\n+ object_property_add_alias(OBJECT(s), bus_name,\n+ OBJECT(&s->spi[i]), \"spi\",\n+ &error_abort);\n+ g_free(bus_name);\n+ }\n+\n+ /* Below devices are not modelled yet. */\n+ create_unimplemented_device(\"i2c_0\", 0x40002000, 0x1000);\n+ create_unimplemented_device(\"dma\", 0x40003000, 0x1000);\n+ create_unimplemented_device(\"watchdog\", 0x40005000, 0x1000);\n+ create_unimplemented_device(\"i2c_1\", 0x40012000, 0x1000);\n+ create_unimplemented_device(\"gpio\", 0x40013000, 0x1000);\n+ create_unimplemented_device(\"hs-dma\", 0x40014000, 0x1000);\n+ create_unimplemented_device(\"can\", 0x40015000, 0x1000);\n+ create_unimplemented_device(\"rtc\", 0x40017000, 0x1000);\n+ create_unimplemented_device(\"apb_config\", 0x40020000, 0x10000);\n+ create_unimplemented_device(\"emac\", 0x40041000, 0x1000);\n+ create_unimplemented_device(\"usb\", 0x40043000, 0x1000);\n+}\n+\n+static Property m2sxxx_soc_properties[] = {\n+ /*\n+ * part name specifies the type of SmartFusion2 device variant(this\n+ * property is for information purpose only.\n+ */\n+ DEFINE_PROP_STRING(\"cpu-type\", MSF2State, cpu_type),\n+ DEFINE_PROP_STRING(\"part-name\", MSF2State, part_name),\n+ DEFINE_PROP_UINT64(\"eNVM-size\", MSF2State, envm_size, MSF2_ENVM_MAX_SIZE),\n+ DEFINE_PROP_UINT64(\"eSRAM-size\", MSF2State, esram_size,\n+ MSF2_ESRAM_MAX_SIZE),\n+ /* Libero GUI shows 100Mhz as default for clocks */\n+ DEFINE_PROP_UINT32(\"m3clk\", MSF2State, m3clk, 100 * 1000000),\n+ /* default divisors in Libero GUI */\n+ DEFINE_PROP_UINT8(\"apb0div\", MSF2State, apb0div, 2),\n+ DEFINE_PROP_UINT8(\"apb1div\", MSF2State, apb1div, 2),\n+ DEFINE_PROP_END_OF_LIST(),\n+};\n+\n+static void m2sxxx_soc_class_init(ObjectClass *klass, void *data)\n+{\n+ DeviceClass *dc = DEVICE_CLASS(klass);\n+\n+ dc->realize = m2sxxx_soc_realize;\n+ dc->props = m2sxxx_soc_properties;\n+}\n+\n+static const TypeInfo m2sxxx_soc_info = {\n+ .name = TYPE_MSF2_SOC,\n+ .parent = TYPE_SYS_BUS_DEVICE,\n+ .instance_size = sizeof(MSF2State),\n+ .instance_init = m2sxxx_soc_initfn,\n+ .class_init = m2sxxx_soc_class_init,\n+};\n+\n+static void m2sxxx_soc_types(void)\n+{\n+ type_register_static(&m2sxxx_soc_info);\n+}\n+\n+type_init(m2sxxx_soc_types)\ndiff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs\nindex 5ee6f7da5b..a6cf24f6ac 100644\n--- a/hw/arm/Makefile.objs\n+++ b/hw/arm/Makefile.objs\n@@ -19,3 +19,4 @@ obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o\n obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o\n obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o\n obj-$(CONFIG_MPS2) += mps2.o\n+obj-$(CONFIG_MSF2) += msf2-soc.o\n","prefixes":["v11","4/5"]}