{"id":816457,"url":"http://patchwork.ozlabs.org/api/patches/816457/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170920201737.25723-2-f4bug@amsat.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170920201737.25723-2-f4bug@amsat.org>","list_archive_url":null,"date":"2017-09-20T20:17:33","name":"[v11,1/5] msf2: Add Smartfusion2 System timer","commit_ref":null,"pull_url":null,"state":"accepted","archived":true,"hash":"0851775e143e0fda1c792f24a935bc211923e13d","submitter":{"id":70924,"url":"http://patchwork.ozlabs.org/api/people/70924/?format=json","name":"Philippe Mathieu-Daudé","email":"f4bug@amsat.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170920201737.25723-2-f4bug@amsat.org/mbox/","series":[{"id":4222,"url":"http://patchwork.ozlabs.org/api/series/4222/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=4222","date":"2017-09-20T20:17:32","name":"Add support for Smartfusion2 SoC","version":11,"mbox":"http://patchwork.ozlabs.org/series/4222/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/816457/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/816457/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400d:c09::241","Subject":"[Qemu-devel] [PATCH v11 1/5] msf2: Add Smartfusion2 System timer","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"From: Subbaraya Sundeep \n\nModelled System Timer in Microsemi's Smartfusion2 Soc.\nTimer has two 32bit down counters and two interrupts.\n\nSigned-off-by: Subbaraya Sundeep \nReviewed-by: Alistair Francis \nAcked-by: Philippe Mathieu-Daudé \nTested-by: Philippe Mathieu-Daudé \n---\n include/hw/timer/mss-timer.h | 64 ++++++++++\n hw/timer/mss-timer.c | 289 +++++++++++++++++++++++++++++++++++++++++++\n hw/timer/Makefile.objs | 1 +\n 3 files changed, 354 insertions(+)\n create mode 100644 include/hw/timer/mss-timer.h\n create mode 100644 hw/timer/mss-timer.c","diff":"diff --git a/include/hw/timer/mss-timer.h b/include/hw/timer/mss-timer.h\nnew file mode 100644\nindex 0000000000..d15d1732f8\n--- /dev/null\n+++ b/include/hw/timer/mss-timer.h\n@@ -0,0 +1,64 @@\n+/*\n+ * Microsemi SmartFusion2 Timer.\n+ *\n+ * Copyright (c) 2017 Subbaraya Sundeep \n+ *\n+ * Permission is hereby granted, free of charge, to any person obtaining a copy\n+ * of this software and associated documentation files (the \"Software\"), to deal\n+ * in the Software without restriction, including without limitation the rights\n+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n+ * copies of the Software, and to permit persons to whom the Software is\n+ * furnished to do so, subject to the following conditions:\n+ *\n+ * The above copyright notice and this permission notice shall be included in\n+ * all copies or substantial portions of the Software.\n+ *\n+ * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n+ * THE SOFTWARE.\n+ */\n+\n+#ifndef HW_MSS_TIMER_H\n+#define HW_MSS_TIMER_H\n+\n+#include \"hw/sysbus.h\"\n+#include \"hw/ptimer.h\"\n+\n+#define TYPE_MSS_TIMER \"mss-timer\"\n+#define MSS_TIMER(obj) OBJECT_CHECK(MSSTimerState, \\\n+ (obj), TYPE_MSS_TIMER)\n+\n+/*\n+ * There are two 32-bit down counting timers.\n+ * Timers 1 and 2 can be concatenated into a single 64-bit Timer\n+ * that operates either in Periodic mode or in One-shot mode.\n+ * Writing 1 to the TIM64_MODE register bit 0 sets the Timers in 64-bit mode.\n+ * In 64-bit mode, writing to the 32-bit registers has no effect.\n+ * Similarly, in 32-bit mode, writing to the 64-bit mode registers\n+ * has no effect. Only two 32-bit timers are supported currently.\n+ */\n+#define NUM_TIMERS 2\n+\n+#define R_TIM1_MAX 6\n+\n+struct Msf2Timer {\n+ QEMUBH *bh;\n+ ptimer_state *ptimer;\n+\n+ uint32_t regs[R_TIM1_MAX];\n+ qemu_irq irq;\n+};\n+\n+typedef struct MSSTimerState {\n+ SysBusDevice parent_obj;\n+\n+ MemoryRegion mmio;\n+ uint32_t freq_hz;\n+ struct Msf2Timer timers[NUM_TIMERS];\n+} MSSTimerState;\n+\n+#endif /* HW_MSS_TIMER_H */\ndiff --git a/hw/timer/mss-timer.c b/hw/timer/mss-timer.c\nnew file mode 100644\nindex 0000000000..60f1213a3b\n--- /dev/null\n+++ b/hw/timer/mss-timer.c\n@@ -0,0 +1,289 @@\n+/*\n+ * Block model of System timer present in\n+ * Microsemi's SmartFusion2 and SmartFusion SoCs.\n+ *\n+ * Copyright (c) 2017 Subbaraya Sundeep .\n+ *\n+ * Permission is hereby granted, free of charge, to any person obtaining a copy\n+ * of this software and associated documentation files (the \"Software\"), to deal\n+ * in the Software without restriction, including without limitation the rights\n+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n+ * copies of the Software, and to permit persons to whom the Software is\n+ * furnished to do so, subject to the following conditions:\n+ *\n+ * The above copyright notice and this permission notice shall be included in\n+ * all copies or substantial portions of the Software.\n+ *\n+ * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n+ * THE SOFTWARE.\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"qemu/main-loop.h\"\n+#include \"qemu/log.h\"\n+#include \"hw/timer/mss-timer.h\"\n+\n+#ifndef MSS_TIMER_ERR_DEBUG\n+#define MSS_TIMER_ERR_DEBUG 0\n+#endif\n+\n+#define DB_PRINT_L(lvl, fmt, args...) do { \\\n+ if (MSS_TIMER_ERR_DEBUG >= lvl) { \\\n+ qemu_log(\"%s: \" fmt \"\\n\", __func__, ## args); \\\n+ } \\\n+} while (0);\n+\n+#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)\n+\n+#define R_TIM_VAL 0\n+#define R_TIM_LOADVAL 1\n+#define R_TIM_BGLOADVAL 2\n+#define R_TIM_CTRL 3\n+#define R_TIM_RIS 4\n+#define R_TIM_MIS 5\n+\n+#define TIMER_CTRL_ENBL (1 << 0)\n+#define TIMER_CTRL_ONESHOT (1 << 1)\n+#define TIMER_CTRL_INTR (1 << 2)\n+#define TIMER_RIS_ACK (1 << 0)\n+#define TIMER_RST_CLR (1 << 6)\n+#define TIMER_MODE (1 << 0)\n+\n+static void timer_update_irq(struct Msf2Timer *st)\n+{\n+ bool isr, ier;\n+\n+ isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK);\n+ ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR);\n+ qemu_set_irq(st->irq, (ier && isr));\n+}\n+\n+static void timer_update(struct Msf2Timer *st)\n+{\n+ uint64_t count;\n+\n+ if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL)) {\n+ ptimer_stop(st->ptimer);\n+ return;\n+ }\n+\n+ count = st->regs[R_TIM_LOADVAL];\n+ ptimer_set_limit(st->ptimer, count, 1);\n+ ptimer_run(st->ptimer, 1);\n+}\n+\n+static uint64_t\n+timer_read(void *opaque, hwaddr offset, unsigned int size)\n+{\n+ MSSTimerState *t = opaque;\n+ hwaddr addr;\n+ struct Msf2Timer *st;\n+ uint32_t ret = 0;\n+ int timer = 0;\n+ int isr;\n+ int ier;\n+\n+ addr = offset >> 2;\n+ /*\n+ * Two independent timers has same base address.\n+ * Based on address passed figure out which timer is being used.\n+ */\n+ if ((addr >= R_TIM1_MAX) && (addr < NUM_TIMERS * R_TIM1_MAX)) {\n+ timer = 1;\n+ addr -= R_TIM1_MAX;\n+ }\n+\n+ st = &t->timers[timer];\n+\n+ switch (addr) {\n+ case R_TIM_VAL:\n+ ret = ptimer_get_count(st->ptimer);\n+ break;\n+\n+ case R_TIM_MIS:\n+ isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK);\n+ ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR);\n+ ret = ier & isr;\n+ break;\n+\n+ default:\n+ if (addr < R_TIM1_MAX) {\n+ ret = st->regs[addr];\n+ } else {\n+ qemu_log_mask(LOG_GUEST_ERROR,\n+ TYPE_MSS_TIMER\": 64-bit mode not supported\\n\");\n+ return ret;\n+ }\n+ break;\n+ }\n+\n+ DB_PRINT(\"timer=%d 0x%\" HWADDR_PRIx \"=0x%\" PRIx32, timer, offset,\n+ ret);\n+ return ret;\n+}\n+\n+static void\n+timer_write(void *opaque, hwaddr offset,\n+ uint64_t val64, unsigned int size)\n+{\n+ MSSTimerState *t = opaque;\n+ hwaddr addr;\n+ struct Msf2Timer *st;\n+ int timer = 0;\n+ uint32_t value = val64;\n+\n+ addr = offset >> 2;\n+ /*\n+ * Two independent timers has same base address.\n+ * Based on addr passed figure out which timer is being used.\n+ */\n+ if ((addr >= R_TIM1_MAX) && (addr < NUM_TIMERS * R_TIM1_MAX)) {\n+ timer = 1;\n+ addr -= R_TIM1_MAX;\n+ }\n+\n+ st = &t->timers[timer];\n+\n+ DB_PRINT(\"addr=0x%\" HWADDR_PRIx \" val=0x%\" PRIx32 \" (timer=%d)\", offset,\n+ value, timer);\n+\n+ switch (addr) {\n+ case R_TIM_CTRL:\n+ st->regs[R_TIM_CTRL] = value;\n+ timer_update(st);\n+ break;\n+\n+ case R_TIM_RIS:\n+ if (value & TIMER_RIS_ACK) {\n+ st->regs[R_TIM_RIS] &= ~TIMER_RIS_ACK;\n+ }\n+ break;\n+\n+ case R_TIM_LOADVAL:\n+ st->regs[R_TIM_LOADVAL] = value;\n+ if (st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL) {\n+ timer_update(st);\n+ }\n+ break;\n+\n+ case R_TIM_BGLOADVAL:\n+ st->regs[R_TIM_BGLOADVAL] = value;\n+ st->regs[R_TIM_LOADVAL] = value;\n+ break;\n+\n+ case R_TIM_VAL:\n+ case R_TIM_MIS:\n+ break;\n+\n+ default:\n+ if (addr < R_TIM1_MAX) {\n+ st->regs[addr] = value;\n+ } else {\n+ qemu_log_mask(LOG_GUEST_ERROR,\n+ TYPE_MSS_TIMER\": 64-bit mode not supported\\n\");\n+ return;\n+ }\n+ break;\n+ }\n+ timer_update_irq(st);\n+}\n+\n+static const MemoryRegionOps timer_ops = {\n+ .read = timer_read,\n+ .write = timer_write,\n+ .endianness = DEVICE_NATIVE_ENDIAN,\n+ .valid = {\n+ .min_access_size = 1,\n+ .max_access_size = 4\n+ }\n+};\n+\n+static void timer_hit(void *opaque)\n+{\n+ struct Msf2Timer *st = opaque;\n+\n+ st->regs[R_TIM_RIS] |= TIMER_RIS_ACK;\n+\n+ if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ONESHOT)) {\n+ timer_update(st);\n+ }\n+ timer_update_irq(st);\n+}\n+\n+static void mss_timer_init(Object *obj)\n+{\n+ MSSTimerState *t = MSS_TIMER(obj);\n+ int i;\n+\n+ /* Init all the ptimers. */\n+ for (i = 0; i < NUM_TIMERS; i++) {\n+ struct Msf2Timer *st = &t->timers[i];\n+\n+ st->bh = qemu_bh_new(timer_hit, st);\n+ st->ptimer = ptimer_init(st->bh, PTIMER_POLICY_DEFAULT);\n+ ptimer_set_freq(st->ptimer, t->freq_hz);\n+ sysbus_init_irq(SYS_BUS_DEVICE(obj), &st->irq);\n+ }\n+\n+ memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, TYPE_MSS_TIMER,\n+ NUM_TIMERS * R_TIM1_MAX * 4);\n+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &t->mmio);\n+}\n+\n+static const VMStateDescription vmstate_timers = {\n+ .name = \"mss-timer-block\",\n+ .version_id = 1,\n+ .minimum_version_id = 1,\n+ .fields = (VMStateField[]) {\n+ VMSTATE_PTIMER(ptimer, struct Msf2Timer),\n+ VMSTATE_UINT32_ARRAY(regs, struct Msf2Timer, R_TIM1_MAX),\n+ VMSTATE_END_OF_LIST()\n+ }\n+};\n+\n+static const VMStateDescription vmstate_mss_timer = {\n+ .name = TYPE_MSS_TIMER,\n+ .version_id = 1,\n+ .minimum_version_id = 1,\n+ .fields = (VMStateField[]) {\n+ VMSTATE_UINT32(freq_hz, MSSTimerState),\n+ VMSTATE_STRUCT_ARRAY(timers, MSSTimerState, NUM_TIMERS, 0,\n+ vmstate_timers, struct Msf2Timer),\n+ VMSTATE_END_OF_LIST()\n+ }\n+};\n+\n+static Property mss_timer_properties[] = {\n+ /* Libero GUI shows 100Mhz as default for clocks */\n+ DEFINE_PROP_UINT32(\"clock-frequency\", MSSTimerState, freq_hz,\n+ 100 * 1000000),\n+ DEFINE_PROP_END_OF_LIST(),\n+};\n+\n+static void mss_timer_class_init(ObjectClass *klass, void *data)\n+{\n+ DeviceClass *dc = DEVICE_CLASS(klass);\n+\n+ dc->props = mss_timer_properties;\n+ dc->vmsd = &vmstate_mss_timer;\n+}\n+\n+static const TypeInfo mss_timer_info = {\n+ .name = TYPE_MSS_TIMER,\n+ .parent = TYPE_SYS_BUS_DEVICE,\n+ .instance_size = sizeof(MSSTimerState),\n+ .instance_init = mss_timer_init,\n+ .class_init = mss_timer_class_init,\n+};\n+\n+static void mss_timer_register_types(void)\n+{\n+ type_register_static(&mss_timer_info);\n+}\n+\n+type_init(mss_timer_register_types)\ndiff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs\nindex 15cce1c531..8c19eac3b6 100644\n--- a/hw/timer/Makefile.objs\n+++ b/hw/timer/Makefile.objs\n@@ -42,3 +42,4 @@ common-obj-$(CONFIG_ASPEED_SOC) += aspeed_timer.o\n \n common-obj-$(CONFIG_SUN4V_RTC) += sun4v-rtc.o\n common-obj-$(CONFIG_CMSDK_APB_TIMER) += cmsdk-apb-timer.o\n+common-obj-$(CONFIG_MSF2) += mss-timer.o\n","prefixes":["v11","1/5"]}