{"id":816432,"url":"http://patchwork.ozlabs.org/api/patches/816432/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170920194934.23071-4-f4bug@amsat.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170920194934.23071-4-f4bug@amsat.org>","list_archive_url":null,"date":"2017-09-20T19:49:31","name":"[v4,3/6] mips: split cpu_mips_realize_env() out of cpu_mips_init()","commit_ref":null,"pull_url":null,"state":"accepted","archived":true,"hash":"ae7871fdb732e22eb69691cba2103a5448d225d3","submitter":{"id":70924,"url":"http://patchwork.ozlabs.org/api/people/70924/?format=json","name":"Philippe Mathieu-Daudé","email":"f4bug@amsat.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170920194934.23071-4-f4bug@amsat.org/mbox/","series":[{"id":4216,"url":"http://patchwork.ozlabs.org/api/series/4216/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=4216","date":"2017-09-20T19:49:28","name":"QOMify MIPS cpu","version":4,"mbox":"http://patchwork.ozlabs.org/series/4216/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/816432/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/816432/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400d:c09::243","Subject":"[Qemu-devel] [PATCH v4 3/6] mips: split cpu_mips_realize_env() out\n\tof cpu_mips_init()","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Thomas Huth , James Hogan ,\n\t=?utf-8?q?Herv=C3=A9_Poussineau?= ,\n\t=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= ,\n\tqemu-devel@nongnu.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"so it can be used in mips_cpu_realizefn() in the next commit\n\nSigned-off-by: Philippe Mathieu-Daudé \nTested-by: Igor Mammedov \nTested-by: James Hogan \nReviewed-by: Eduardo Habkost \n---\n target/mips/internal.h | 1 +\n target/mips/translate.c | 19 ++++++++++++-------\n 2 files changed, 13 insertions(+), 7 deletions(-)","diff":"diff --git a/target/mips/internal.h b/target/mips/internal.h\nindex 91c2df4537..cf4c9db427 100644\n--- a/target/mips/internal.h\n+++ b/target/mips/internal.h\n@@ -132,6 +132,7 @@ void mips_tcg_init(void);\n \n /* TODO QOM'ify CPU reset and remove */\n void cpu_state_reset(CPUMIPSState *s);\n+void cpu_mips_realize_env(CPUMIPSState *env);\n \n /* cp0_timer.c */\n uint32_t cpu_mips_get_random(CPUMIPSState *env);\ndiff --git a/target/mips/translate.c b/target/mips/translate.c\nindex f0febaf1b2..5fc7979ac5 100644\n--- a/target/mips/translate.c\n+++ b/target/mips/translate.c\n@@ -20512,6 +20512,17 @@ void mips_tcg_init(void)\n \n #include \"translate_init.c\"\n \n+void cpu_mips_realize_env(CPUMIPSState *env)\n+{\n+ env->exception_base = (int32_t)0xBFC00000;\n+\n+#ifndef CONFIG_USER_ONLY\n+ mmu_init(env, env->cpu_model);\n+#endif\n+ fpu_init(env, env->cpu_model);\n+ mvp_init(env, env->cpu_model);\n+}\n+\n MIPSCPU *cpu_mips_init(const char *cpu_model)\n {\n MIPSCPU *cpu;\n@@ -20524,13 +20535,7 @@ MIPSCPU *cpu_mips_init(const char *cpu_model)\n cpu = MIPS_CPU(object_new(TYPE_MIPS_CPU));\n env = &cpu->env;\n env->cpu_model = def;\n- env->exception_base = (int32_t)0xBFC00000;\n-\n-#ifndef CONFIG_USER_ONLY\n- mmu_init(env, def);\n-#endif\n- fpu_init(env, def);\n- mvp_init(env, def);\n+ cpu_mips_realize_env(env);\n \n object_property_set_bool(OBJECT(cpu), true, \"realized\", NULL);\n \n","prefixes":["v4","3/6"]}