{"id":816431,"url":"http://patchwork.ozlabs.org/api/patches/816431/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170920194934.23071-5-f4bug@amsat.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170920194934.23071-5-f4bug@amsat.org>","list_archive_url":null,"date":"2017-09-20T19:49:32","name":"[v4,4/6] mips: call cpu_mips_realize_env() from mips_cpu_realizefn()","commit_ref":null,"pull_url":null,"state":"accepted","archived":true,"hash":"173a3805a639cff3cc5778c25ccc431df20f76af","submitter":{"id":70924,"url":"http://patchwork.ozlabs.org/api/people/70924/?format=json","name":"Philippe Mathieu-Daudé","email":"f4bug@amsat.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170920194934.23071-5-f4bug@amsat.org/mbox/","series":[{"id":4216,"url":"http://patchwork.ozlabs.org/api/series/4216/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=4216","date":"2017-09-20T19:49:28","name":"QOMify MIPS cpu","version":4,"mbox":"http://patchwork.ozlabs.org/series/4216/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/816431/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/816431/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400d:c09::243","Subject":"[Qemu-devel] [PATCH v4 4/6] mips: call cpu_mips_realize_env() from\n\tmips_cpu_realizefn()","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Thomas Huth , James Hogan ,\n\t=?utf-8?q?Herv=C3=A9_Poussineau?= ,\n\t=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= ,\n\tqemu-devel@nongnu.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"This changes the order between cpu_mips_realize_env() and\ncpu_exec_initfn(), but cpu_exec_initfn() don't have anything that\ndepends on cpu_mips_realize_env() being called first.\n\nSigned-off-by: Philippe Mathieu-Daudé \nTested-by: Igor Mammedov \nTested-by: James Hogan \nReviewed-by: Eduardo Habkost \n---\n target/mips/cpu.c | 3 +++\n target/mips/translate.c | 1 -\n 2 files changed, 3 insertions(+), 1 deletion(-)","diff":"diff --git a/target/mips/cpu.c b/target/mips/cpu.c\nindex 68bf423e9d..e3ef835599 100644\n--- a/target/mips/cpu.c\n+++ b/target/mips/cpu.c\n@@ -123,6 +123,7 @@ static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info) {\n static void mips_cpu_realizefn(DeviceState *dev, Error **errp)\n {\n CPUState *cs = CPU(dev);\n+ MIPSCPU *cpu = MIPS_CPU(dev);\n MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(dev);\n Error *local_err = NULL;\n \n@@ -132,6 +133,8 @@ static void mips_cpu_realizefn(DeviceState *dev, Error **errp)\n return;\n }\n \n+ cpu_mips_realize_env(&cpu->env);\n+\n cpu_reset(cs);\n qemu_init_vcpu(cs);\n \ndiff --git a/target/mips/translate.c b/target/mips/translate.c\nindex 5fc7979ac5..94c38e8755 100644\n--- a/target/mips/translate.c\n+++ b/target/mips/translate.c\n@@ -20535,7 +20535,6 @@ MIPSCPU *cpu_mips_init(const char *cpu_model)\n cpu = MIPS_CPU(object_new(TYPE_MIPS_CPU));\n env = &cpu->env;\n env->cpu_model = def;\n- cpu_mips_realize_env(env);\n \n object_property_set_bool(OBJECT(cpu), true, \"realized\", NULL);\n \n","prefixes":["v4","4/6"]}