{"id":816225,"url":"http://patchwork.ozlabs.org/api/patches/816225/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20170920133927.17390-6-jbrunet@baylibre.com/","project":{"id":42,"url":"http://patchwork.ozlabs.org/api/projects/42/?format=json","name":"Linux GPIO development","link_name":"linux-gpio","list_id":"linux-gpio.vger.kernel.org","list_email":"linux-gpio@vger.kernel.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170920133927.17390-6-jbrunet@baylibre.com>","list_archive_url":null,"date":"2017-09-20T13:39:24","name":"[5/8] pinctrl: meson: remove offset continued - meson8b","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"fcf5ac210436e580ebffa7d6c8edb698a442d0cf","submitter":{"id":69839,"url":"http://patchwork.ozlabs.org/api/people/69839/?format=json","name":"Jerome Brunet","email":"jbrunet@baylibre.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20170920133927.17390-6-jbrunet@baylibre.com/mbox/","series":[{"id":4115,"url":"http://patchwork.ozlabs.org/api/series/4115/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/list/?series=4115","date":"2017-09-20T13:39:19","name":"pinctrl: meson: clean pin offsets","version":1,"mbox":"http://patchwork.ozlabs.org/series/4115/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/816225/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/816225/checks/","tags":{},"related":[],"headers":{"Return-Path":"<linux-gpio-owner@vger.kernel.org>","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=baylibre-com.20150623.gappssmtp.com\n\theader.i=@baylibre-com.20150623.gappssmtp.com\n\theader.b=\"y97nx24u\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xy19C0TtJz9sP1\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 20 Sep 2017 23:41:03 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751762AbdITNkd (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tWed, 20 Sep 2017 09:40:33 -0400","from mail-wr0-f177.google.com ([209.85.128.177]:52673 \"EHLO\n\tmail-wr0-f177.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751697AbdITNjo (ORCPT\n\t<rfc822; linux-gpio@vger.kernel.org>); Wed, 20 Sep 2017 09:39:44 -0400","by mail-wr0-f177.google.com with SMTP id c23so2186820wrg.9\n\tfor <linux-gpio@vger.kernel.org>;\n\tWed, 20 Sep 2017 06:39:43 -0700 (PDT)","from localhost.localdomain ([90.63.244.31])\n\tby smtp.googlemail.com with ESMTPSA id\n\ta39sm1938888wrc.48.2017.09.20.06.39.40\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tWed, 20 Sep 2017 06:39:41 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=baylibre-com.20150623.gappssmtp.com; s=20150623;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=+DXw1nKIZ0CbGqOPHOQ47uj1GiF9hnH7oV3ULc0brWc=;\n\tb=y97nx24uSlIop6pad4k4p84CFWWdjBaYMfVYli3djaIA9JAqceiLnUM/MfTfE0KfZT\n\tuZt0DTFuz36oTagVB5q6ohmmWlQH12WT7XCb1tllvHGrjJuZWVYQQNsxEjXXA86Mw/X3\n\tnUcM6nhHo0xg9I40dYLstyfOCONXw8prFtr2IvAd5IQnhcsTk5EFSmiqLbwCWKIJ8HwO\n\trckCPhHVWmvBheZ3ajzfRIAHGyqni94qYesTZIFFm+fuIwy/8VYoGJiC/taJ9Q8tukgG\n\tqDXJqwsoqogRN2xM+ZKt8NDom+B/kbKKyuYzodJ+66u8RO2dM3cl4qj02Qpwcg9w/s7d\n\tSSkA==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=+DXw1nKIZ0CbGqOPHOQ47uj1GiF9hnH7oV3ULc0brWc=;\n\tb=Qfq5a/tGEkpbKF5ItLAdnx1wWCgsTY1FWHF+A7+qkN0OebFB5szJDBbgaW4MLqyKmj\n\tkE8QMmigDxU5qK4lxiXtCzChSNA0cIp/kf0/snVJ61RIH6ApW74YHO+4rd2tmZ6jaEvP\n\t9ahPMA+wZdxQJggTbMQU1poGAXOeJLO5CFzhU729NJbNkLHSncJeMKhpYm49CTOIXPwG\n\tcNgatNxQqwdP9UYHVljzyr5tW1mslRsQKggkILij4/Zs/tDl2N+hxb4ONOFuKfibHXpF\n\txUcle7JVgYVV8ErqzaPupK577jwDZobvAAlyJNa4S1Asz6hJQV4xb5NIJILfhU8LmcV1\n\tIc/Q==","X-Gm-Message-State":"AHPjjUiAog5POyMwOqYnL26w+Ul00pJML/+DeA8FbG02pxbIC+VODPDZ\n\toFtwchVNUDNjxofb36zuEmah/w==","X-Google-Smtp-Source":"AOwi7QCHKfHT5Z+EnJKF8FAHB5W7Manko71jmFZL/+YzUDFmplQx+Y9KjbfBaMqZjqTrQeMz9mlLow==","X-Received":"by 10.223.166.138 with SMTP id t10mr4898238wrc.64.1505914781996; \n\tWed, 20 Sep 2017 06:39:41 -0700 (PDT)","From":"Jerome Brunet <jbrunet@baylibre.com>","To":"Linus Walleij <linus.walleij@linaro.org>,\n\tKevin Hilman <khilman@baylibre.com>, Carlo Caione <carlo@caione.org>","Cc":"Jerome Brunet <jbrunet@baylibre.com>, linux-gpio@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org,\n\tlinux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org,\n\tdevicetree@vger.kernel.org,\n\tMartin Blumenstingl <martin.blumenstingl@googlemail.com>","Subject":"[PATCH 5/8] pinctrl: meson: remove offset continued - meson8b","Date":"Wed, 20 Sep 2017 15:39:24 +0200","Message-Id":"<20170920133927.17390-6-jbrunet@baylibre.com>","X-Mailer":"git-send-email 2.13.5","In-Reply-To":"<20170920133927.17390-1-jbrunet@baylibre.com>","References":"<20170920133927.17390-1-jbrunet@baylibre.com>","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"<linux-gpio.vger.kernel.org>","X-Mailing-List":"linux-gpio@vger.kernel.org"},"content":"Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>\nSigned-off-by: Jerome Brunet <jbrunet@baylibre.com>\n---\n drivers/pinctrl/meson/pinctrl-meson8b.c | 780 ++++++++++++++++----------------\n 1 file changed, 388 insertions(+), 392 deletions(-)","diff":"diff --git a/drivers/pinctrl/meson/pinctrl-meson8b.c b/drivers/pinctrl/meson/pinctrl-meson8b.c\nindex 71f216b5b0b9..c3c247bfbc60 100644\n--- a/drivers/pinctrl/meson/pinctrl-meson8b.c\n+++ b/drivers/pinctrl/meson/pinctrl-meson8b.c\n@@ -15,407 +15,403 @@\n #include <dt-bindings/gpio/meson8b-gpio.h>\n #include \"pinctrl-meson.h\"\n \n-#define AO_OFF\t130\n-\n static const struct pinctrl_pin_desc meson8b_cbus_pins[] = {\n-\tMESON_PIN(GPIOX_0, 0),\n-\tMESON_PIN(GPIOX_1, 0),\n-\tMESON_PIN(GPIOX_2, 0),\n-\tMESON_PIN(GPIOX_3, 0),\n-\tMESON_PIN(GPIOX_4, 0),\n-\tMESON_PIN(GPIOX_5, 0),\n-\tMESON_PIN(GPIOX_6, 0),\n-\tMESON_PIN(GPIOX_7, 0),\n-\tMESON_PIN(GPIOX_8, 0),\n-\tMESON_PIN(GPIOX_9, 0),\n-\tMESON_PIN(GPIOX_10, 0),\n-\tMESON_PIN(GPIOX_11, 0),\n-\tMESON_PIN(GPIOX_16, 0),\n-\tMESON_PIN(GPIOX_17, 0),\n-\tMESON_PIN(GPIOX_18, 0),\n-\tMESON_PIN(GPIOX_19, 0),\n-\tMESON_PIN(GPIOX_20, 0),\n-\tMESON_PIN(GPIOX_21, 0),\n-\n-\tMESON_PIN(GPIOY_0, 0),\n-\tMESON_PIN(GPIOY_1, 0),\n-\tMESON_PIN(GPIOY_3, 0),\n-\tMESON_PIN(GPIOY_6, 0),\n-\tMESON_PIN(GPIOY_7, 0),\n-\tMESON_PIN(GPIOY_8, 0),\n-\tMESON_PIN(GPIOY_9, 0),\n-\tMESON_PIN(GPIOY_10, 0),\n-\tMESON_PIN(GPIOY_11, 0),\n-\tMESON_PIN(GPIOY_12, 0),\n-\tMESON_PIN(GPIOY_13, 0),\n-\tMESON_PIN(GPIOY_14, 0),\n-\n-\tMESON_PIN(GPIODV_9, 0),\n-\tMESON_PIN(GPIODV_24, 0),\n-\tMESON_PIN(GPIODV_25, 0),\n-\tMESON_PIN(GPIODV_26, 0),\n-\tMESON_PIN(GPIODV_27, 0),\n-\tMESON_PIN(GPIODV_28, 0),\n-\tMESON_PIN(GPIODV_29, 0),\n-\n-\tMESON_PIN(GPIOH_0, 0),\n-\tMESON_PIN(GPIOH_1, 0),\n-\tMESON_PIN(GPIOH_2, 0),\n-\tMESON_PIN(GPIOH_3, 0),\n-\tMESON_PIN(GPIOH_4, 0),\n-\tMESON_PIN(GPIOH_5, 0),\n-\tMESON_PIN(GPIOH_6, 0),\n-\tMESON_PIN(GPIOH_7, 0),\n-\tMESON_PIN(GPIOH_8, 0),\n-\tMESON_PIN(GPIOH_9, 0),\n-\n-\tMESON_PIN(CARD_0, 0),\n-\tMESON_PIN(CARD_1, 0),\n-\tMESON_PIN(CARD_2, 0),\n-\tMESON_PIN(CARD_3, 0),\n-\tMESON_PIN(CARD_4, 0),\n-\tMESON_PIN(CARD_5, 0),\n-\tMESON_PIN(CARD_6, 0),\n-\n-\tMESON_PIN(BOOT_0, 0),\n-\tMESON_PIN(BOOT_1, 0),\n-\tMESON_PIN(BOOT_2, 0),\n-\tMESON_PIN(BOOT_3, 0),\n-\tMESON_PIN(BOOT_4, 0),\n-\tMESON_PIN(BOOT_5, 0),\n-\tMESON_PIN(BOOT_6, 0),\n-\tMESON_PIN(BOOT_7, 0),\n-\tMESON_PIN(BOOT_8, 0),\n-\tMESON_PIN(BOOT_9, 0),\n-\tMESON_PIN(BOOT_10, 0),\n-\tMESON_PIN(BOOT_11, 0),\n-\tMESON_PIN(BOOT_12, 0),\n-\tMESON_PIN(BOOT_13, 0),\n-\tMESON_PIN(BOOT_14, 0),\n-\tMESON_PIN(BOOT_15, 0),\n-\tMESON_PIN(BOOT_16, 0),\n-\tMESON_PIN(BOOT_17, 0),\n-\tMESON_PIN(BOOT_18, 0),\n-\n-\tMESON_PIN(DIF_0_P, 0),\n-\tMESON_PIN(DIF_0_N, 0),\n-\tMESON_PIN(DIF_1_P, 0),\n-\tMESON_PIN(DIF_1_N, 0),\n-\tMESON_PIN(DIF_2_P, 0),\n-\tMESON_PIN(DIF_2_N, 0),\n-\tMESON_PIN(DIF_3_P, 0),\n-\tMESON_PIN(DIF_3_N, 0),\n-\tMESON_PIN(DIF_4_P, 0),\n-\tMESON_PIN(DIF_4_N, 0),\n+\tMESON_PIN(GPIOX_0),\n+\tMESON_PIN(GPIOX_1),\n+\tMESON_PIN(GPIOX_2),\n+\tMESON_PIN(GPIOX_3),\n+\tMESON_PIN(GPIOX_4),\n+\tMESON_PIN(GPIOX_5),\n+\tMESON_PIN(GPIOX_6),\n+\tMESON_PIN(GPIOX_7),\n+\tMESON_PIN(GPIOX_8),\n+\tMESON_PIN(GPIOX_9),\n+\tMESON_PIN(GPIOX_10),\n+\tMESON_PIN(GPIOX_11),\n+\tMESON_PIN(GPIOX_16),\n+\tMESON_PIN(GPIOX_17),\n+\tMESON_PIN(GPIOX_18),\n+\tMESON_PIN(GPIOX_19),\n+\tMESON_PIN(GPIOX_20),\n+\tMESON_PIN(GPIOX_21),\n+\n+\tMESON_PIN(GPIOY_0),\n+\tMESON_PIN(GPIOY_1),\n+\tMESON_PIN(GPIOY_3),\n+\tMESON_PIN(GPIOY_6),\n+\tMESON_PIN(GPIOY_7),\n+\tMESON_PIN(GPIOY_8),\n+\tMESON_PIN(GPIOY_9),\n+\tMESON_PIN(GPIOY_10),\n+\tMESON_PIN(GPIOY_11),\n+\tMESON_PIN(GPIOY_12),\n+\tMESON_PIN(GPIOY_13),\n+\tMESON_PIN(GPIOY_14),\n+\n+\tMESON_PIN(GPIODV_9),\n+\tMESON_PIN(GPIODV_24),\n+\tMESON_PIN(GPIODV_25),\n+\tMESON_PIN(GPIODV_26),\n+\tMESON_PIN(GPIODV_27),\n+\tMESON_PIN(GPIODV_28),\n+\tMESON_PIN(GPIODV_29),\n+\n+\tMESON_PIN(GPIOH_0),\n+\tMESON_PIN(GPIOH_1),\n+\tMESON_PIN(GPIOH_2),\n+\tMESON_PIN(GPIOH_3),\n+\tMESON_PIN(GPIOH_4),\n+\tMESON_PIN(GPIOH_5),\n+\tMESON_PIN(GPIOH_6),\n+\tMESON_PIN(GPIOH_7),\n+\tMESON_PIN(GPIOH_8),\n+\tMESON_PIN(GPIOH_9),\n+\n+\tMESON_PIN(CARD_0),\n+\tMESON_PIN(CARD_1),\n+\tMESON_PIN(CARD_2),\n+\tMESON_PIN(CARD_3),\n+\tMESON_PIN(CARD_4),\n+\tMESON_PIN(CARD_5),\n+\tMESON_PIN(CARD_6),\n+\n+\tMESON_PIN(BOOT_0),\n+\tMESON_PIN(BOOT_1),\n+\tMESON_PIN(BOOT_2),\n+\tMESON_PIN(BOOT_3),\n+\tMESON_PIN(BOOT_4),\n+\tMESON_PIN(BOOT_5),\n+\tMESON_PIN(BOOT_6),\n+\tMESON_PIN(BOOT_7),\n+\tMESON_PIN(BOOT_8),\n+\tMESON_PIN(BOOT_9),\n+\tMESON_PIN(BOOT_10),\n+\tMESON_PIN(BOOT_11),\n+\tMESON_PIN(BOOT_12),\n+\tMESON_PIN(BOOT_13),\n+\tMESON_PIN(BOOT_14),\n+\tMESON_PIN(BOOT_15),\n+\tMESON_PIN(BOOT_16),\n+\tMESON_PIN(BOOT_17),\n+\tMESON_PIN(BOOT_18),\n+\n+\tMESON_PIN(DIF_0_P),\n+\tMESON_PIN(DIF_0_N),\n+\tMESON_PIN(DIF_1_P),\n+\tMESON_PIN(DIF_1_N),\n+\tMESON_PIN(DIF_2_P),\n+\tMESON_PIN(DIF_2_N),\n+\tMESON_PIN(DIF_3_P),\n+\tMESON_PIN(DIF_3_N),\n+\tMESON_PIN(DIF_4_P),\n+\tMESON_PIN(DIF_4_N),\n };\n \n static const struct pinctrl_pin_desc meson8b_aobus_pins[] = {\n-\tMESON_PIN(GPIOAO_0, AO_OFF),\n-\tMESON_PIN(GPIOAO_1, AO_OFF),\n-\tMESON_PIN(GPIOAO_2, AO_OFF),\n-\tMESON_PIN(GPIOAO_3, AO_OFF),\n-\tMESON_PIN(GPIOAO_4, AO_OFF),\n-\tMESON_PIN(GPIOAO_5, AO_OFF),\n-\tMESON_PIN(GPIOAO_6, AO_OFF),\n-\tMESON_PIN(GPIOAO_7, AO_OFF),\n-\tMESON_PIN(GPIOAO_8, AO_OFF),\n-\tMESON_PIN(GPIOAO_9, AO_OFF),\n-\tMESON_PIN(GPIOAO_10, AO_OFF),\n-\tMESON_PIN(GPIOAO_11, AO_OFF),\n-\tMESON_PIN(GPIOAO_12, AO_OFF),\n-\tMESON_PIN(GPIOAO_13, AO_OFF),\n+\tMESON_PIN(GPIOAO_0),\n+\tMESON_PIN(GPIOAO_1),\n+\tMESON_PIN(GPIOAO_2),\n+\tMESON_PIN(GPIOAO_3),\n+\tMESON_PIN(GPIOAO_4),\n+\tMESON_PIN(GPIOAO_5),\n+\tMESON_PIN(GPIOAO_6),\n+\tMESON_PIN(GPIOAO_7),\n+\tMESON_PIN(GPIOAO_8),\n+\tMESON_PIN(GPIOAO_9),\n+\tMESON_PIN(GPIOAO_10),\n+\tMESON_PIN(GPIOAO_11),\n+\tMESON_PIN(GPIOAO_12),\n+\tMESON_PIN(GPIOAO_13),\n \n \t/*\n \t * The following 2 pins are not mentionned in the public datasheet\n \t * According to this datasheet, they can't be used with the gpio\n \t * interrupt controller\n \t */\n-\tMESON_PIN(GPIO_BSD_EN, AO_OFF),\n-\tMESON_PIN(GPIO_TEST_N, AO_OFF),\n+\tMESON_PIN(GPIO_BSD_EN),\n+\tMESON_PIN(GPIO_TEST_N),\n };\n \n /* bank X */\n-static const unsigned int sd_d0_a_pins[]\t= { PIN(GPIOX_0, 0) };\n-static const unsigned int sd_d1_a_pins[]\t= { PIN(GPIOX_1, 0) };\n-static const unsigned int sd_d2_a_pins[]\t= { PIN(GPIOX_2, 0) };\n-static const unsigned int sd_d3_a_pins[]\t= { PIN(GPIOX_3, 0) };\n-static const unsigned int sdxc_d0_0_a_pins[]\t= { PIN(GPIOX_4, 0) };\n-static const unsigned int sdxc_d47_a_pins[]\t= { PIN(GPIOX_4, 0), PIN(GPIOX_5, 0),\n-\t\t\t\t\t\t    PIN(GPIOX_6, 0), PIN(GPIOX_7, 0) };\n-static const unsigned int sdxc_d13_0_a_pins[]\t= { PIN(GPIOX_5, 0), PIN(GPIOX_6, 0),\n-\t\t\t\t\t\t    PIN(GPIOX_7, 0) };\n-static const unsigned int sd_clk_a_pins[]\t= { PIN(GPIOX_8, 0) };\n-static const unsigned int sd_cmd_a_pins[]\t= { PIN(GPIOX_9, 0) };\n-static const unsigned int xtal_32k_out_pins[]\t= { PIN(GPIOX_10, 0) };\n-static const unsigned int xtal_24m_out_pins[]\t= { PIN(GPIOX_11, 0) };\n-static const unsigned int uart_tx_b0_pins[]\t= { PIN(GPIOX_16, 0) };\n-static const unsigned int uart_rx_b0_pins[]\t= { PIN(GPIOX_17, 0) };\n-static const unsigned int uart_cts_b0_pins[]\t= { PIN(GPIOX_18, 0) };\n-static const unsigned int uart_rts_b0_pins[]\t= { PIN(GPIOX_19, 0) };\n-\n-static const unsigned int sdxc_d0_1_a_pins[]\t= { PIN(GPIOX_0, 0) };\n-static const unsigned int sdxc_d13_1_a_pins[]\t= { PIN(GPIOX_1, 0), PIN(GPIOX_2, 0),\n-\t\t\t\t\t\t    PIN(GPIOX_3, 0) };\n-static const unsigned int pcm_out_a_pins[]\t= { PIN(GPIOX_4, 0) };\n-static const unsigned int pcm_in_a_pins[]\t= { PIN(GPIOX_5, 0) };\n-static const unsigned int pcm_fs_a_pins[]\t= { PIN(GPIOX_6, 0) };\n-static const unsigned int pcm_clk_a_pins[]\t= { PIN(GPIOX_7, 0) };\n-static const unsigned int sdxc_clk_a_pins[]\t= { PIN(GPIOX_8, 0) };\n-static const unsigned int sdxc_cmd_a_pins[]\t= { PIN(GPIOX_9, 0) };\n-static const unsigned int pwm_vs_0_pins[]\t= { PIN(GPIOX_10, 0) };\n-static const unsigned int pwm_e_pins[]\t\t= { PIN(GPIOX_10, 0) };\n-static const unsigned int pwm_vs_1_pins[]\t= { PIN(GPIOX_11, 0) };\n-\n-static const unsigned int uart_tx_a_pins[]\t= { PIN(GPIOX_4, 0) };\n-static const unsigned int uart_rx_a_pins[]\t= { PIN(GPIOX_5, 0) };\n-static const unsigned int uart_cts_a_pins[]\t= { PIN(GPIOX_6, 0) };\n-static const unsigned int uart_rts_a_pins[]\t= { PIN(GPIOX_7, 0) };\n-static const unsigned int uart_tx_b1_pins[]\t= { PIN(GPIOX_8, 0) };\n-static const unsigned int uart_rx_b1_pins[]\t= { PIN(GPIOX_9, 0) };\n-static const unsigned int uart_cts_b1_pins[]\t= { PIN(GPIOX_10, 0) };\n-static const unsigned int uart_rts_b1_pins[]\t= { PIN(GPIOX_20, 0) };\n-\n-static const unsigned int iso7816_0_clk_pins[]\t= { PIN(GPIOX_6, 0) };\n-static const unsigned int iso7816_0_data_pins[]\t= { PIN(GPIOX_7, 0) };\n-static const unsigned int spi_sclk_0_pins[]\t= { PIN(GPIOX_8, 0) };\n-static const unsigned int spi_miso_0_pins[]\t= { PIN(GPIOX_9, 0) };\n-static const unsigned int spi_mosi_0_pins[]\t= { PIN(GPIOX_10, 0) };\n-static const unsigned int iso7816_det_pins[]\t= { PIN(GPIOX_16, 0) };\n-static const unsigned int iso7816_reset_pins[]\t= { PIN(GPIOX_17, 0) };\n-static const unsigned int iso7816_1_clk_pins[]\t= { PIN(GPIOX_18, 0) };\n-static const unsigned int iso7816_1_data_pins[]\t= { PIN(GPIOX_19, 0) };\n-static const unsigned int spi_ss0_0_pins[]\t= { PIN(GPIOX_20, 0) };\n-\n-static const unsigned int tsin_clk_b_pins[]\t= { PIN(GPIOX_8, 0) };\n-static const unsigned int tsin_sop_b_pins[]\t= { PIN(GPIOX_9, 0) };\n-static const unsigned int tsin_d0_b_pins[]\t= { PIN(GPIOX_10, 0) };\n-static const unsigned int pwm_b_pins[]\t\t= { PIN(GPIOX_11, 0) };\n-static const unsigned int i2c_sda_d0_pins[]\t= { PIN(GPIOX_16, 0) };\n-static const unsigned int i2c_sck_d0_pins[]\t= { PIN(GPIOX_17, 0) };\n-static const unsigned int tsin_d_valid_b_pins[] = { PIN(GPIOX_20, 0) };\n+static const unsigned int sd_d0_a_pins[]\t= { GPIOX_0 };\n+static const unsigned int sd_d1_a_pins[]\t= { GPIOX_1 };\n+static const unsigned int sd_d2_a_pins[]\t= { GPIOX_2 };\n+static const unsigned int sd_d3_a_pins[]\t= { GPIOX_3 };\n+static const unsigned int sdxc_d0_0_a_pins[]\t= { GPIOX_4 };\n+static const unsigned int sdxc_d47_a_pins[]\t= { GPIOX_4, GPIOX_5,\n+\t\t\t\t\t\t    GPIOX_6, GPIOX_7 };\n+static const unsigned int sdxc_d13_0_a_pins[]\t= { GPIOX_5, GPIOX_6,\n+\t\t\t\t\t\t    GPIOX_7 };\n+static const unsigned int sd_clk_a_pins[]\t= { GPIOX_8 };\n+static const unsigned int sd_cmd_a_pins[]\t= { GPIOX_9 };\n+static const unsigned int xtal_32k_out_pins[]\t= { GPIOX_10 };\n+static const unsigned int xtal_24m_out_pins[]\t= { GPIOX_11 };\n+static const unsigned int uart_tx_b0_pins[]\t= { GPIOX_16 };\n+static const unsigned int uart_rx_b0_pins[]\t= { GPIOX_17 };\n+static const unsigned int uart_cts_b0_pins[]\t= { GPIOX_18 };\n+static const unsigned int uart_rts_b0_pins[]\t= { GPIOX_19 };\n+\n+static const unsigned int sdxc_d0_1_a_pins[]\t= { GPIOX_0 };\n+static const unsigned int sdxc_d13_1_a_pins[]\t= { GPIOX_1, GPIOX_2,\n+\t\t\t\t\t\t    GPIOX_3 };\n+static const unsigned int pcm_out_a_pins[]\t= { GPIOX_4 };\n+static const unsigned int pcm_in_a_pins[]\t= { GPIOX_5 };\n+static const unsigned int pcm_fs_a_pins[]\t= { GPIOX_6 };\n+static const unsigned int pcm_clk_a_pins[]\t= { GPIOX_7 };\n+static const unsigned int sdxc_clk_a_pins[]\t= { GPIOX_8 };\n+static const unsigned int sdxc_cmd_a_pins[]\t= { GPIOX_9 };\n+static const unsigned int pwm_vs_0_pins[]\t= { GPIOX_10 };\n+static const unsigned int pwm_e_pins[]\t\t= { GPIOX_10 };\n+static const unsigned int pwm_vs_1_pins[]\t= { GPIOX_11 };\n+\n+static const unsigned int uart_tx_a_pins[]\t= { GPIOX_4 };\n+static const unsigned int uart_rx_a_pins[]\t= { GPIOX_5 };\n+static const unsigned int uart_cts_a_pins[]\t= { GPIOX_6 };\n+static const unsigned int uart_rts_a_pins[]\t= { GPIOX_7 };\n+static const unsigned int uart_tx_b1_pins[]\t= { GPIOX_8 };\n+static const unsigned int uart_rx_b1_pins[]\t= { GPIOX_9 };\n+static const unsigned int uart_cts_b1_pins[]\t= { GPIOX_10 };\n+static const unsigned int uart_rts_b1_pins[]\t= { GPIOX_20 };\n+\n+static const unsigned int iso7816_0_clk_pins[]\t= { GPIOX_6 };\n+static const unsigned int iso7816_0_data_pins[]\t= { GPIOX_7 };\n+static const unsigned int spi_sclk_0_pins[]\t= { GPIOX_8 };\n+static const unsigned int spi_miso_0_pins[]\t= { GPIOX_9 };\n+static const unsigned int spi_mosi_0_pins[]\t= { GPIOX_10 };\n+static const unsigned int iso7816_det_pins[]\t= { GPIOX_16 };\n+static const unsigned int iso7816_reset_pins[]\t= { GPIOX_17 };\n+static const unsigned int iso7816_1_clk_pins[]\t= { GPIOX_18 };\n+static const unsigned int iso7816_1_data_pins[]\t= { GPIOX_19 };\n+static const unsigned int spi_ss0_0_pins[]\t= { GPIOX_20 };\n+\n+static const unsigned int tsin_clk_b_pins[]\t= { GPIOX_8 };\n+static const unsigned int tsin_sop_b_pins[]\t= { GPIOX_9 };\n+static const unsigned int tsin_d0_b_pins[]\t= { GPIOX_10 };\n+static const unsigned int pwm_b_pins[]\t\t= { GPIOX_11 };\n+static const unsigned int i2c_sda_d0_pins[]\t= { GPIOX_16 };\n+static const unsigned int i2c_sck_d0_pins[]\t= { GPIOX_17 };\n+static const unsigned int tsin_d_valid_b_pins[] = { GPIOX_20 };\n \n /* bank Y */\n-static const unsigned int tsin_d_valid_a_pins[] = { PIN(GPIOY_0, 0) };\n-static const unsigned int tsin_sop_a_pins[]\t= { PIN(GPIOY_1, 0) };\n-static const unsigned int tsin_d17_a_pins[]\t= { PIN(GPIOY_6, 0), PIN(GPIOY_7, 0),\n-\t\t\t\t\t\t    PIN(GPIOY_10, 0), PIN(GPIOY_11, 0),\n-\t\t\t\t\t\t    PIN(GPIOY_12, 0), PIN(GPIOY_13, 0),\n-\t\t\t\t\t\t    PIN(GPIOY_14, 0) };\n-static const unsigned int tsin_clk_a_pins[]\t= { PIN(GPIOY_8, 0) };\n-static const unsigned int tsin_d0_a_pins[]\t= { PIN(GPIOY_9, 0) };\n+static const unsigned int tsin_d_valid_a_pins[] = { GPIOY_0 };\n+static const unsigned int tsin_sop_a_pins[]\t= { GPIOY_1 };\n+static const unsigned int tsin_d17_a_pins[] = {\n+\tGPIOY_6, GPIOY_7, GPIOY_10, GPIOY_11, GPIOY_12, GPIOY_13, GPIOY_14,\n+};\n+static const unsigned int tsin_clk_a_pins[]\t= { GPIOY_8 };\n+static const unsigned int tsin_d0_a_pins[]\t= { GPIOY_9 };\n \n-static const unsigned int spdif_out_0_pins[]\t= { PIN(GPIOY_3, 0) };\n+static const unsigned int spdif_out_0_pins[]\t= { GPIOY_3 };\n \n-static const unsigned int xtal_24m_pins[]\t= { PIN(GPIOY_3, 0) };\n-static const unsigned int iso7816_2_clk_pins[]\t= { PIN(GPIOY_13, 0) };\n-static const unsigned int iso7816_2_data_pins[] = { PIN(GPIOY_14, 0) };\n+static const unsigned int xtal_24m_pins[]\t= { GPIOY_3 };\n+static const unsigned int iso7816_2_clk_pins[]\t= { GPIOY_13 };\n+static const unsigned int iso7816_2_data_pins[] = { GPIOY_14 };\n \n /* bank DV */\n-static const unsigned int pwm_d_pins[]\t\t= { PIN(GPIODV_28, 0) };\n-static const unsigned int pwm_c0_pins[]\t\t= { PIN(GPIODV_29, 0) };\n+static const unsigned int pwm_d_pins[]\t\t= { GPIODV_28 };\n+static const unsigned int pwm_c0_pins[]\t\t= { GPIODV_29 };\n \n-static const unsigned int pwm_vs_2_pins[]\t= { PIN(GPIODV_9, 0) };\n-static const unsigned int pwm_vs_3_pins[]\t= { PIN(GPIODV_28, 0) };\n-static const unsigned int pwm_vs_4_pins[]\t= { PIN(GPIODV_29, 0) };\n+static const unsigned int pwm_vs_2_pins[]\t= { GPIODV_9 };\n+static const unsigned int pwm_vs_3_pins[]\t= { GPIODV_28 };\n+static const unsigned int pwm_vs_4_pins[]\t= { GPIODV_29 };\n \n-static const unsigned int xtal24_out_pins[]\t= { PIN(GPIODV_29, 0) };\n+static const unsigned int xtal24_out_pins[]\t= { GPIODV_29 };\n \n-static const unsigned int uart_tx_c_pins[]\t= { PIN(GPIODV_24, 0) };\n-static const unsigned int uart_rx_c_pins[]\t= { PIN(GPIODV_25, 0) };\n-static const unsigned int uart_cts_c_pins[]\t= { PIN(GPIODV_26, 0) };\n-static const unsigned int uart_rts_c_pins[]\t= { PIN(GPIODV_27, 0) };\n+static const unsigned int uart_tx_c_pins[]\t= { GPIODV_24 };\n+static const unsigned int uart_rx_c_pins[]\t= { GPIODV_25 };\n+static const unsigned int uart_cts_c_pins[]\t= { GPIODV_26 };\n+static const unsigned int uart_rts_c_pins[]\t= { GPIODV_27 };\n \n-static const unsigned int pwm_c1_pins[]\t\t= { PIN(GPIODV_9, 0) };\n+static const unsigned int pwm_c1_pins[]\t\t= { GPIODV_9 };\n \n-static const unsigned int i2c_sda_a_pins[]\t= { PIN(GPIODV_24, 0) };\n-static const unsigned int i2c_sck_a_pins[]\t= { PIN(GPIODV_25, 0) };\n-static const unsigned int i2c_sda_b0_pins[]\t= { PIN(GPIODV_26, 0) };\n-static const unsigned int i2c_sck_b0_pins[]\t= { PIN(GPIODV_27, 0) };\n-static const unsigned int i2c_sda_c0_pins[]\t= { PIN(GPIODV_28, 0) };\n-static const unsigned int i2c_sck_c0_pins[]\t= { PIN(GPIODV_29, 0) };\n+static const unsigned int i2c_sda_a_pins[]\t= { GPIODV_24 };\n+static const unsigned int i2c_sck_a_pins[]\t= { GPIODV_25 };\n+static const unsigned int i2c_sda_b0_pins[]\t= { GPIODV_26 };\n+static const unsigned int i2c_sck_b0_pins[]\t= { GPIODV_27 };\n+static const unsigned int i2c_sda_c0_pins[]\t= { GPIODV_28 };\n+static const unsigned int i2c_sck_c0_pins[]\t= { GPIODV_29 };\n \n /* bank H */\n-static const unsigned int hdmi_hpd_pins[]\t= { PIN(GPIOH_0, 0) };\n-static const unsigned int hdmi_sda_pins[]\t= { PIN(GPIOH_1, 0) };\n-static const unsigned int hdmi_scl_pins[]\t= { PIN(GPIOH_2, 0) };\n-static const unsigned int hdmi_cec_0_pins[]\t= { PIN(GPIOH_3, 0) };\n-static const unsigned int eth_txd1_0_pins[]\t= { PIN(GPIOH_5, 0) };\n-static const unsigned int eth_txd0_0_pins[]\t= { PIN(GPIOH_6, 0) };\n-static const unsigned int clk_24m_out_pins[]\t= { PIN(GPIOH_9, 0) };\n-\n-static const unsigned int spi_ss1_pins[]\t= { PIN(GPIOH_0, 0) };\n-static const unsigned int spi_ss2_pins[]\t= { PIN(GPIOH_1, 0) };\n-static const unsigned int spi_ss0_1_pins[]\t= { PIN(GPIOH_3, 0) };\n-static const unsigned int spi_miso_1_pins[]\t= { PIN(GPIOH_4, 0) };\n-static const unsigned int spi_mosi_1_pins[]\t= { PIN(GPIOH_5, 0) };\n-static const unsigned int spi_sclk_1_pins[]\t= { PIN(GPIOH_6, 0) };\n-\n-static const unsigned int eth_txd3_pins[]\t= { PIN(GPIOH_7, 0) };\n-static const unsigned int eth_txd2_pins[]\t= { PIN(GPIOH_8, 0) };\n-static const unsigned int eth_tx_clk_pins[]\t= { PIN(GPIOH_9, 0) };\n-\n-static const unsigned int i2c_sda_b1_pins[]\t= { PIN(GPIOH_3, 0) };\n-static const unsigned int i2c_sck_b1_pins[]\t= { PIN(GPIOH_4, 0) };\n-static const unsigned int i2c_sda_c1_pins[]\t= { PIN(GPIOH_5, 0) };\n-static const unsigned int i2c_sck_c1_pins[]\t= { PIN(GPIOH_6, 0) };\n-static const unsigned int i2c_sda_d1_pins[]\t= { PIN(GPIOH_7, 0) };\n-static const unsigned int i2c_sck_d1_pins[]\t= { PIN(GPIOH_8, 0) };\n+static const unsigned int hdmi_hpd_pins[]\t= { GPIOH_0 };\n+static const unsigned int hdmi_sda_pins[]\t= { GPIOH_1 };\n+static const unsigned int hdmi_scl_pins[]\t= { GPIOH_2 };\n+static const unsigned int hdmi_cec_0_pins[]\t= { GPIOH_3 };\n+static const unsigned int eth_txd1_0_pins[]\t= { GPIOH_5 };\n+static const unsigned int eth_txd0_0_pins[]\t= { GPIOH_6 };\n+static const unsigned int clk_24m_out_pins[]\t= { GPIOH_9 };\n+\n+static const unsigned int spi_ss1_pins[]\t= { GPIOH_0 };\n+static const unsigned int spi_ss2_pins[]\t= { GPIOH_1 };\n+static const unsigned int spi_ss0_1_pins[]\t= { GPIOH_3 };\n+static const unsigned int spi_miso_1_pins[]\t= { GPIOH_4 };\n+static const unsigned int spi_mosi_1_pins[]\t= { GPIOH_5 };\n+static const unsigned int spi_sclk_1_pins[]\t= { GPIOH_6 };\n+\n+static const unsigned int eth_txd3_pins[]\t= { GPIOH_7 };\n+static const unsigned int eth_txd2_pins[]\t= { GPIOH_8 };\n+static const unsigned int eth_tx_clk_pins[]\t= { GPIOH_9 };\n+\n+static const unsigned int i2c_sda_b1_pins[]\t= { GPIOH_3 };\n+static const unsigned int i2c_sck_b1_pins[]\t= { GPIOH_4 };\n+static const unsigned int i2c_sda_c1_pins[]\t= { GPIOH_5 };\n+static const unsigned int i2c_sck_c1_pins[]\t= { GPIOH_6 };\n+static const unsigned int i2c_sda_d1_pins[]\t= { GPIOH_7 };\n+static const unsigned int i2c_sck_d1_pins[]\t= { GPIOH_8 };\n \n /* bank BOOT */\n-static const unsigned int nand_io_pins[]\t= { PIN(BOOT_0, 0), PIN(BOOT_1, 0),\n-\t\t\t\t\t\t    PIN(BOOT_2, 0), PIN(BOOT_3, 0),\n-\t\t\t\t\t\t    PIN(BOOT_4, 0), PIN(BOOT_5, 0),\n-\t\t\t\t\t\t    PIN(BOOT_6, 0), PIN(BOOT_7, 0) };\n-static const unsigned int nand_io_ce0_pins[]\t= { PIN(BOOT_8, 0) };\n-static const unsigned int nand_io_ce1_pins[]\t= { PIN(BOOT_9, 0) };\n-static const unsigned int nand_io_rb0_pins[]\t= { PIN(BOOT_10, 0) };\n-static const unsigned int nand_ale_pins[]\t= { PIN(BOOT_11, 0) };\n-static const unsigned int nand_cle_pins[]\t= { PIN(BOOT_12, 0) };\n-static const unsigned int nand_wen_clk_pins[]\t= { PIN(BOOT_13, 0) };\n-static const unsigned int nand_ren_clk_pins[]\t= { PIN(BOOT_14, 0) };\n-static const unsigned int nand_dqs_15_pins[]\t= { PIN(BOOT_15, 0) };\n-static const unsigned int nand_dqs_18_pins[]\t= { PIN(BOOT_18, 0) };\n-\n-static const unsigned int sdxc_d0_c_pins[]\t= { PIN(BOOT_0, 0)};\n-static const unsigned int sdxc_d13_c_pins[]\t= { PIN(BOOT_1, 0), PIN(BOOT_2, 0),\n-\t\t\t\t\t\t    PIN(BOOT_3, 0) };\n-static const unsigned int sdxc_d47_c_pins[]\t= { PIN(BOOT_4, 0), PIN(BOOT_5, 0),\n-\t\t\t\t\t\t    PIN(BOOT_6, 0), PIN(BOOT_7, 0) };\n-static const unsigned int sdxc_clk_c_pins[]\t= { PIN(BOOT_8, 0) };\n-static const unsigned int sdxc_cmd_c_pins[]\t= { PIN(BOOT_10, 0) };\n-static const unsigned int nor_d_pins[]\t\t= { PIN(BOOT_11, 0) };\n-static const unsigned int nor_q_pins[]\t\t= { PIN(BOOT_12, 0) };\n-static const unsigned int nor_c_pins[]\t\t= { PIN(BOOT_13, 0) };\n-static const unsigned int nor_cs_pins[]\t\t= { PIN(BOOT_18, 0) };\n-\n-static const unsigned int sd_d0_c_pins[]\t= { PIN(BOOT_0, 0) };\n-static const unsigned int sd_d1_c_pins[]\t= { PIN(BOOT_1, 0) };\n-static const unsigned int sd_d2_c_pins[]\t= { PIN(BOOT_2, 0) };\n-static const unsigned int sd_d3_c_pins[]\t= { PIN(BOOT_3, 0) };\n-static const unsigned int sd_cmd_c_pins[]\t= { PIN(BOOT_8, 0) };\n-static const unsigned int sd_clk_c_pins[]\t= { PIN(BOOT_10, 0) };\n+static const unsigned int nand_io_pins[] = {\n+\tBOOT_0, BOOT_1, BOOT_2, BOOT_3, BOOT_4, BOOT_5, BOOT_6, BOOT_7\n+};\n+static const unsigned int nand_io_ce0_pins[]\t= { BOOT_8 };\n+static const unsigned int nand_io_ce1_pins[]\t= { BOOT_9 };\n+static const unsigned int nand_io_rb0_pins[]\t= { BOOT_10 };\n+static const unsigned int nand_ale_pins[]\t= { BOOT_11 };\n+static const unsigned int nand_cle_pins[]\t= { BOOT_12 };\n+static const unsigned int nand_wen_clk_pins[]\t= { BOOT_13 };\n+static const unsigned int nand_ren_clk_pins[]\t= { BOOT_14 };\n+static const unsigned int nand_dqs_15_pins[]\t= { BOOT_15 };\n+static const unsigned int nand_dqs_18_pins[]\t= { BOOT_18 };\n+\n+static const unsigned int sdxc_d0_c_pins[]\t= { BOOT_0};\n+static const unsigned int sdxc_d13_c_pins[]\t= { BOOT_1, BOOT_2,\n+\t\t\t\t\t\t    BOOT_3 };\n+static const unsigned int sdxc_d47_c_pins[]\t= { BOOT_4, BOOT_5,\n+\t\t\t\t\t\t    BOOT_6, BOOT_7 };\n+static const unsigned int sdxc_clk_c_pins[]\t= { BOOT_8 };\n+static const unsigned int sdxc_cmd_c_pins[]\t= { BOOT_10 };\n+static const unsigned int nor_d_pins[]\t\t= { BOOT_11 };\n+static const unsigned int nor_q_pins[]\t\t= { BOOT_12 };\n+static const unsigned int nor_c_pins[]\t\t= { BOOT_13 };\n+static const unsigned int nor_cs_pins[]\t\t= { BOOT_18 };\n+\n+static const unsigned int sd_d0_c_pins[]\t= { BOOT_0 };\n+static const unsigned int sd_d1_c_pins[]\t= { BOOT_1 };\n+static const unsigned int sd_d2_c_pins[]\t= { BOOT_2 };\n+static const unsigned int sd_d3_c_pins[]\t= { BOOT_3 };\n+static const unsigned int sd_cmd_c_pins[]\t= { BOOT_8 };\n+static const unsigned int sd_clk_c_pins[]\t= { BOOT_10 };\n \n /* bank CARD */\n-static const unsigned int sd_d1_b_pins[]\t= { PIN(CARD_0, 0) };\n-static const unsigned int sd_d0_b_pins[]\t= { PIN(CARD_1, 0) };\n-static const unsigned int sd_clk_b_pins[]\t= { PIN(CARD_2, 0) };\n-static const unsigned int sd_cmd_b_pins[]\t= { PIN(CARD_3, 0) };\n-static const unsigned int sd_d3_b_pins[]\t= { PIN(CARD_4, 0) };\n-static const unsigned int sd_d2_b_pins[]\t= { PIN(CARD_5, 0) };\n-\n-static const unsigned int sdxc_d13_b_pins[]\t= { PIN(CARD_0, 0), PIN(CARD_4, 0),\n-\t\t\t\t\t\t    PIN(CARD_5, 0) };\n-static const unsigned int sdxc_d0_b_pins[]\t= { PIN(CARD_1, 0) };\n-static const unsigned int sdxc_clk_b_pins[]\t= { PIN(CARD_2, 0) };\n-static const unsigned int sdxc_cmd_b_pins[]\t= { PIN(CARD_3, 0) };\n+static const unsigned int sd_d1_b_pins[]\t= { CARD_0 };\n+static const unsigned int sd_d0_b_pins[]\t= { CARD_1 };\n+static const unsigned int sd_clk_b_pins[]\t= { CARD_2 };\n+static const unsigned int sd_cmd_b_pins[]\t= { CARD_3 };\n+static const unsigned int sd_d3_b_pins[]\t= { CARD_4 };\n+static const unsigned int sd_d2_b_pins[]\t= { CARD_5 };\n+\n+static const unsigned int sdxc_d13_b_pins[]\t= { CARD_0,  CARD_4,\n+\t\t\t\t\t\t    CARD_5 };\n+static const unsigned int sdxc_d0_b_pins[]\t= { CARD_1 };\n+static const unsigned int sdxc_clk_b_pins[]\t= { CARD_2 };\n+static const unsigned int sdxc_cmd_b_pins[]\t= { CARD_3 };\n \n /* bank AO */\n-static const unsigned int uart_tx_ao_a_pins[]\t= { PIN(GPIOAO_0, AO_OFF) };\n-static const unsigned int uart_rx_ao_a_pins[]\t= { PIN(GPIOAO_1, AO_OFF) };\n-static const unsigned int uart_cts_ao_a_pins[]\t= { PIN(GPIOAO_2, AO_OFF) };\n-static const unsigned int uart_rts_ao_a_pins[]\t= { PIN(GPIOAO_3, AO_OFF) };\n-static const unsigned int i2c_mst_sck_ao_pins[] = { PIN(GPIOAO_4, AO_OFF) };\n-static const unsigned int i2c_mst_sda_ao_pins[] = { PIN(GPIOAO_5, AO_OFF) };\n-static const unsigned int clk_32k_in_out_pins[]\t= { PIN(GPIOAO_6, AO_OFF) };\n-static const unsigned int remote_input_pins[]\t= { PIN(GPIOAO_7, AO_OFF) };\n-static const unsigned int hdmi_cec_1_pins[]\t= { PIN(GPIOAO_12, AO_OFF) };\n-static const unsigned int ir_blaster_pins[]\t= { PIN(GPIOAO_13, AO_OFF) };\n-\n-static const unsigned int pwm_c2_pins[]\t\t= { PIN(GPIOAO_3, AO_OFF) };\n-static const unsigned int i2c_sck_ao_pins[]\t= { PIN(GPIOAO_4, AO_OFF) };\n-static const unsigned int i2c_sda_ao_pins[]\t= { PIN(GPIOAO_5, AO_OFF) };\n-static const unsigned int ir_remote_out_pins[]\t= { PIN(GPIOAO_7, AO_OFF) };\n-static const unsigned int i2s_am_clk_out_pins[]\t= { PIN(GPIOAO_8, AO_OFF) };\n-static const unsigned int i2s_ao_clk_out_pins[]\t= { PIN(GPIOAO_9, AO_OFF) };\n-static const unsigned int i2s_lr_clk_out_pins[]\t= { PIN(GPIOAO_10, AO_OFF) };\n-static const unsigned int i2s_out_01_pins[]\t= { PIN(GPIOAO_11, AO_OFF) };\n-\n-static const unsigned int uart_tx_ao_b0_pins[]\t= { PIN(GPIOAO_0, AO_OFF) };\n-static const unsigned int uart_rx_ao_b0_pins[]\t= { PIN(GPIOAO_1, AO_OFF) };\n-static const unsigned int uart_cts_ao_b_pins[]\t= { PIN(GPIOAO_2, AO_OFF) };\n-static const unsigned int uart_rts_ao_b_pins[]\t= { PIN(GPIOAO_3, AO_OFF) };\n-static const unsigned int uart_tx_ao_b1_pins[]\t= { PIN(GPIOAO_4, AO_OFF) };\n-static const unsigned int uart_rx_ao_b1_pins[]\t= { PIN(GPIOAO_5, AO_OFF) };\n-static const unsigned int spdif_out_1_pins[]\t= { PIN(GPIOAO_6, AO_OFF) };\n-\n-static const unsigned int i2s_in_ch01_pins[]\t= { PIN(GPIOAO_6, AO_OFF) };\n-static const unsigned int i2s_ao_clk_in_pins[]\t= { PIN(GPIOAO_9, AO_OFF) };\n-static const unsigned int i2s_lr_clk_in_pins[]\t= { PIN(GPIOAO_10, AO_OFF) };\n+static const unsigned int uart_tx_ao_a_pins[]\t= { GPIOAO_0 };\n+static const unsigned int uart_rx_ao_a_pins[]\t= { GPIOAO_1 };\n+static const unsigned int uart_cts_ao_a_pins[]\t= { GPIOAO_2 };\n+static const unsigned int uart_rts_ao_a_pins[]\t= { GPIOAO_3 };\n+static const unsigned int i2c_mst_sck_ao_pins[] = { GPIOAO_4 };\n+static const unsigned int i2c_mst_sda_ao_pins[] = { GPIOAO_5 };\n+static const unsigned int clk_32k_in_out_pins[]\t= { GPIOAO_6 };\n+static const unsigned int remote_input_pins[]\t= { GPIOAO_7 };\n+static const unsigned int hdmi_cec_1_pins[]\t= { GPIOAO_12 };\n+static const unsigned int ir_blaster_pins[]\t= { GPIOAO_13 };\n+\n+static const unsigned int pwm_c2_pins[]\t\t= { GPIOAO_3 };\n+static const unsigned int i2c_sck_ao_pins[]\t= { GPIOAO_4 };\n+static const unsigned int i2c_sda_ao_pins[]\t= { GPIOAO_5 };\n+static const unsigned int ir_remote_out_pins[]\t= { GPIOAO_7 };\n+static const unsigned int i2s_am_clk_out_pins[]\t= { GPIOAO_8 };\n+static const unsigned int i2s_ao_clk_out_pins[]\t= { GPIOAO_9 };\n+static const unsigned int i2s_lr_clk_out_pins[]\t= { GPIOAO_10 };\n+static const unsigned int i2s_out_01_pins[]\t= { GPIOAO_11 };\n+\n+static const unsigned int uart_tx_ao_b0_pins[]\t= { GPIOAO_0 };\n+static const unsigned int uart_rx_ao_b0_pins[]\t= { GPIOAO_1 };\n+static const unsigned int uart_cts_ao_b_pins[]\t= { GPIOAO_2 };\n+static const unsigned int uart_rts_ao_b_pins[]\t= { GPIOAO_3 };\n+static const unsigned int uart_tx_ao_b1_pins[]\t= { GPIOAO_4 };\n+static const unsigned int uart_rx_ao_b1_pins[]\t= { GPIOAO_5 };\n+static const unsigned int spdif_out_1_pins[]\t= { GPIOAO_6 };\n+\n+static const unsigned int i2s_in_ch01_pins[]\t= { GPIOAO_6 };\n+static const unsigned int i2s_ao_clk_in_pins[]\t= { GPIOAO_9 };\n+static const unsigned int i2s_lr_clk_in_pins[]\t= { GPIOAO_10 };\n \n /* bank DIF */\n-static const unsigned int eth_rxd1_pins[]\t= { PIN(DIF_0_P, 0) };\n-static const unsigned int eth_rxd0_pins[]\t= { PIN(DIF_0_N, 0) };\n-static const unsigned int eth_rx_dv_pins[]\t= { PIN(DIF_1_P, 0) };\n-static const unsigned int eth_rx_clk_pins[]\t= { PIN(DIF_1_N, 0) };\n-static const unsigned int eth_txd0_1_pins[]\t= { PIN(DIF_2_P, 0) };\n-static const unsigned int eth_txd1_1_pins[]\t= { PIN(DIF_2_N, 0) };\n-static const unsigned int eth_tx_en_pins[]\t= { PIN(DIF_3_P, 0) };\n-static const unsigned int eth_ref_clk_pins[]\t= { PIN(DIF_3_N, 0) };\n-static const unsigned int eth_mdc_pins[]\t= { PIN(DIF_4_P, 0) };\n-static const unsigned int eth_mdio_en_pins[]\t= { PIN(DIF_4_N, 0) };\n+static const unsigned int eth_rxd1_pins[]\t= { DIF_0_P };\n+static const unsigned int eth_rxd0_pins[]\t= { DIF_0_N };\n+static const unsigned int eth_rx_dv_pins[]\t= { DIF_1_P };\n+static const unsigned int eth_rx_clk_pins[]\t= { DIF_1_N };\n+static const unsigned int eth_txd0_1_pins[]\t= { DIF_2_P };\n+static const unsigned int eth_txd1_1_pins[]\t= { DIF_2_N };\n+static const unsigned int eth_tx_en_pins[]\t= { DIF_3_P };\n+static const unsigned int eth_ref_clk_pins[]\t= { DIF_3_N };\n+static const unsigned int eth_mdc_pins[]\t= { DIF_4_P };\n+static const unsigned int eth_mdio_en_pins[]\t= { DIF_4_N };\n \n static struct meson_pmx_group meson8b_cbus_groups[] = {\n-\tGPIO_GROUP(GPIOX_0, 0),\n-\tGPIO_GROUP(GPIOX_1, 0),\n-\tGPIO_GROUP(GPIOX_2, 0),\n-\tGPIO_GROUP(GPIOX_3, 0),\n-\tGPIO_GROUP(GPIOX_4, 0),\n-\tGPIO_GROUP(GPIOX_5, 0),\n-\tGPIO_GROUP(GPIOX_6, 0),\n-\tGPIO_GROUP(GPIOX_7, 0),\n-\tGPIO_GROUP(GPIOX_8, 0),\n-\tGPIO_GROUP(GPIOX_9, 0),\n-\tGPIO_GROUP(GPIOX_10, 0),\n-\tGPIO_GROUP(GPIOX_11, 0),\n-\tGPIO_GROUP(GPIOX_16, 0),\n-\tGPIO_GROUP(GPIOX_17, 0),\n-\tGPIO_GROUP(GPIOX_18, 0),\n-\tGPIO_GROUP(GPIOX_19, 0),\n-\tGPIO_GROUP(GPIOX_20, 0),\n-\tGPIO_GROUP(GPIOX_21, 0),\n-\n-\tGPIO_GROUP(GPIOY_0, 0),\n-\tGPIO_GROUP(GPIOY_1, 0),\n-\tGPIO_GROUP(GPIOY_3, 0),\n-\tGPIO_GROUP(GPIOY_6, 0),\n-\tGPIO_GROUP(GPIOY_7, 0),\n-\tGPIO_GROUP(GPIOY_8, 0),\n-\tGPIO_GROUP(GPIOY_9, 0),\n-\tGPIO_GROUP(GPIOY_10, 0),\n-\tGPIO_GROUP(GPIOY_11, 0),\n-\tGPIO_GROUP(GPIOY_12, 0),\n-\tGPIO_GROUP(GPIOY_13, 0),\n-\tGPIO_GROUP(GPIOY_14, 0),\n-\n-\tGPIO_GROUP(GPIODV_9, 0),\n-\tGPIO_GROUP(GPIODV_24, 0),\n-\tGPIO_GROUP(GPIODV_25, 0),\n-\tGPIO_GROUP(GPIODV_26, 0),\n-\tGPIO_GROUP(GPIODV_27, 0),\n-\tGPIO_GROUP(GPIODV_28, 0),\n-\tGPIO_GROUP(GPIODV_29, 0),\n-\n-\tGPIO_GROUP(GPIOH_0, 0),\n-\tGPIO_GROUP(GPIOH_1, 0),\n-\tGPIO_GROUP(GPIOH_2, 0),\n-\tGPIO_GROUP(GPIOH_3, 0),\n-\tGPIO_GROUP(GPIOH_4, 0),\n-\tGPIO_GROUP(GPIOH_5, 0),\n-\tGPIO_GROUP(GPIOH_6, 0),\n-\tGPIO_GROUP(GPIOH_7, 0),\n-\tGPIO_GROUP(GPIOH_8, 0),\n-\tGPIO_GROUP(GPIOH_9, 0),\n-\n-\tGPIO_GROUP(DIF_0_P, 0),\n-\tGPIO_GROUP(DIF_0_N, 0),\n-\tGPIO_GROUP(DIF_1_P, 0),\n-\tGPIO_GROUP(DIF_1_N, 0),\n-\tGPIO_GROUP(DIF_2_P, 0),\n-\tGPIO_GROUP(DIF_2_N, 0),\n-\tGPIO_GROUP(DIF_3_P, 0),\n-\tGPIO_GROUP(DIF_3_N, 0),\n-\tGPIO_GROUP(DIF_4_P, 0),\n-\tGPIO_GROUP(DIF_4_N, 0),\n+\tGPIO_GROUP(GPIOX_0),\n+\tGPIO_GROUP(GPIOX_1),\n+\tGPIO_GROUP(GPIOX_2),\n+\tGPIO_GROUP(GPIOX_3),\n+\tGPIO_GROUP(GPIOX_4),\n+\tGPIO_GROUP(GPIOX_5),\n+\tGPIO_GROUP(GPIOX_6),\n+\tGPIO_GROUP(GPIOX_7),\n+\tGPIO_GROUP(GPIOX_8),\n+\tGPIO_GROUP(GPIOX_9),\n+\tGPIO_GROUP(GPIOX_10),\n+\tGPIO_GROUP(GPIOX_11),\n+\tGPIO_GROUP(GPIOX_16),\n+\tGPIO_GROUP(GPIOX_17),\n+\tGPIO_GROUP(GPIOX_18),\n+\tGPIO_GROUP(GPIOX_19),\n+\tGPIO_GROUP(GPIOX_20),\n+\tGPIO_GROUP(GPIOX_21),\n+\n+\tGPIO_GROUP(GPIOY_0),\n+\tGPIO_GROUP(GPIOY_1),\n+\tGPIO_GROUP(GPIOY_3),\n+\tGPIO_GROUP(GPIOY_6),\n+\tGPIO_GROUP(GPIOY_7),\n+\tGPIO_GROUP(GPIOY_8),\n+\tGPIO_GROUP(GPIOY_9),\n+\tGPIO_GROUP(GPIOY_10),\n+\tGPIO_GROUP(GPIOY_11),\n+\tGPIO_GROUP(GPIOY_12),\n+\tGPIO_GROUP(GPIOY_13),\n+\tGPIO_GROUP(GPIOY_14),\n+\n+\tGPIO_GROUP(GPIODV_9),\n+\tGPIO_GROUP(GPIODV_24),\n+\tGPIO_GROUP(GPIODV_25),\n+\tGPIO_GROUP(GPIODV_26),\n+\tGPIO_GROUP(GPIODV_27),\n+\tGPIO_GROUP(GPIODV_28),\n+\tGPIO_GROUP(GPIODV_29),\n+\n+\tGPIO_GROUP(GPIOH_0),\n+\tGPIO_GROUP(GPIOH_1),\n+\tGPIO_GROUP(GPIOH_2),\n+\tGPIO_GROUP(GPIOH_3),\n+\tGPIO_GROUP(GPIOH_4),\n+\tGPIO_GROUP(GPIOH_5),\n+\tGPIO_GROUP(GPIOH_6),\n+\tGPIO_GROUP(GPIOH_7),\n+\tGPIO_GROUP(GPIOH_8),\n+\tGPIO_GROUP(GPIOH_9),\n+\n+\tGPIO_GROUP(DIF_0_P),\n+\tGPIO_GROUP(DIF_0_N),\n+\tGPIO_GROUP(DIF_1_P),\n+\tGPIO_GROUP(DIF_1_N),\n+\tGPIO_GROUP(DIF_2_P),\n+\tGPIO_GROUP(DIF_2_N),\n+\tGPIO_GROUP(DIF_3_P),\n+\tGPIO_GROUP(DIF_3_N),\n+\tGPIO_GROUP(DIF_4_P),\n+\tGPIO_GROUP(DIF_4_N),\n \n \t/* bank X */\n \tGROUP(sd_d0_a,\t\t8,\t5),\n@@ -577,22 +573,22 @@ static struct meson_pmx_group meson8b_cbus_groups[] = {\n };\n \n static struct meson_pmx_group meson8b_aobus_groups[] = {\n-\tGPIO_GROUP(GPIOAO_0, AO_OFF),\n-\tGPIO_GROUP(GPIOAO_1, AO_OFF),\n-\tGPIO_GROUP(GPIOAO_2, AO_OFF),\n-\tGPIO_GROUP(GPIOAO_3, AO_OFF),\n-\tGPIO_GROUP(GPIOAO_4, AO_OFF),\n-\tGPIO_GROUP(GPIOAO_5, AO_OFF),\n-\tGPIO_GROUP(GPIOAO_6, AO_OFF),\n-\tGPIO_GROUP(GPIOAO_7, AO_OFF),\n-\tGPIO_GROUP(GPIOAO_8, AO_OFF),\n-\tGPIO_GROUP(GPIOAO_9, AO_OFF),\n-\tGPIO_GROUP(GPIOAO_10, AO_OFF),\n-\tGPIO_GROUP(GPIOAO_11, AO_OFF),\n-\tGPIO_GROUP(GPIOAO_12, AO_OFF),\n-\tGPIO_GROUP(GPIOAO_13, AO_OFF),\n-\tGPIO_GROUP(GPIO_BSD_EN, AO_OFF),\n-\tGPIO_GROUP(GPIO_TEST_N, AO_OFF),\n+\tGPIO_GROUP(GPIOAO_0),\n+\tGPIO_GROUP(GPIOAO_1),\n+\tGPIO_GROUP(GPIOAO_2),\n+\tGPIO_GROUP(GPIOAO_3),\n+\tGPIO_GROUP(GPIOAO_4),\n+\tGPIO_GROUP(GPIOAO_5),\n+\tGPIO_GROUP(GPIOAO_6),\n+\tGPIO_GROUP(GPIOAO_7),\n+\tGPIO_GROUP(GPIOAO_8),\n+\tGPIO_GROUP(GPIOAO_9),\n+\tGPIO_GROUP(GPIOAO_10),\n+\tGPIO_GROUP(GPIOAO_11),\n+\tGPIO_GROUP(GPIOAO_12),\n+\tGPIO_GROUP(GPIOAO_13),\n+\tGPIO_GROUP(GPIO_BSD_EN),\n+\tGPIO_GROUP(GPIO_TEST_N),\n \n \t/* bank AO */\n \tGROUP(uart_tx_ao_a,\t0,\t12),\n@@ -887,25 +883,25 @@ static struct meson_pmx_func meson8b_aobus_functions[] = {\n };\n \n static struct meson_bank meson8b_cbus_banks[] = {\n-\t/*   name    first                      last                irq      pullen  pull    dir     out     in  */\n-\tBANK(\"X\",    PIN(GPIOX_0, 0),\t\tPIN(GPIOX_21, 0),   97, 118, 4,  0,  4,  0,  0,  0,  1,  0,  2,  0),\n-\tBANK(\"Y\",    PIN(GPIOY_0, 0),\t\tPIN(GPIOY_14, 0),   80,  96, 3,  0,  3,  0,  3,  0,  4,  0,  5,  0),\n-\tBANK(\"DV\",   PIN(GPIODV_9, 0),\t\tPIN(GPIODV_29, 0),  59,  79, 0,  0,  0,  0,  7,  0,  8,  0,  9,  0),\n-\tBANK(\"H\",    PIN(GPIOH_0, 0),\t\tPIN(GPIOH_9, 0),    14,  23, 1, 16,  1, 16,  9, 19, 10, 19, 11, 19),\n-\tBANK(\"CARD\", PIN(CARD_0, 0),\t\tPIN(CARD_6, 0),     43,  49, 2, 20,  2, 20,  0, 22,  1, 22,  2, 22),\n-\tBANK(\"BOOT\", PIN(BOOT_0, 0),\t\tPIN(BOOT_18, 0),    24,  42, 2,  0,  2,  0,  9,  0, 10,  0, 11,  0),\n+\t/*   name    first              last        irq      pullen  pull    dir     out     in  */\n+\tBANK(\"X\",    GPIOX_0,\t\tGPIOX_21,   97, 118, 4,  0,  4,  0,  0,  0,  1,  0,  2,  0),\n+\tBANK(\"Y\",    GPIOY_0,\t\tGPIOY_14,   80,  96, 3,  0,  3,  0,  3,  0,  4,  0,  5,  0),\n+\tBANK(\"DV\",   GPIODV_9,\t\tGPIODV_29,  59,  79, 0,  0,  0,  0,  7,  0,  8,  0,  9,  0),\n+\tBANK(\"H\",    GPIOH_0,\t\tGPIOH_9,    14,  23, 1, 16,  1, 16,  9, 19, 10, 19, 11, 19),\n+\tBANK(\"CARD\", CARD_0,\t\tCARD_6,     43,  49, 2, 20,  2, 20,  0, 22,  1, 22,  2, 22),\n+\tBANK(\"BOOT\", BOOT_0,\t\tBOOT_18,    24,  42, 2,  0,  2,  0,  9,  0, 10,  0, 11,  0),\n \n \t/*\n \t * The following bank is not mentionned in the public datasheet\n \t * There is no information whether it can be used with the gpio\n \t * interrupt controller\n \t */\n-\tBANK(\"DIF\",  PIN(DIF_0_P, 0),\t\tPIN(DIF_4_N, 0),    -1,  -1, 5,  8,  5,  8, 12, 12, 13, 12, 14, 12),\n+\tBANK(\"DIF\",  DIF_0_P,\t\tDIF_4_N,    -1,  -1, 5,  8,  5,  8, 12, 12, 13, 12, 14, 12),\n };\n \n static struct meson_bank meson8b_aobus_banks[] = {\n-\t/*   name    first                  last                      irq    pullen  pull    dir     out     in  */\n-\tBANK(\"AO\",   PIN(GPIOAO_0, AO_OFF), PIN(GPIO_TEST_N, AO_OFF), 0, 13, 0,  0,  0, 16,  0,  0,  0, 16,  1,  0),\n+\t/*   name    first     lastc        irq    pullen  pull    dir     out     in  */\n+\tBANK(\"AO\",   GPIOAO_0, GPIO_TEST_N, 0, 13, 0,  0,  0, 16,  0,  0,  0, 16,  1,  0),\n };\n \n struct meson_pinctrl_data meson8b_cbus_pinctrl_data = {\n@@ -923,7 +919,7 @@ struct meson_pinctrl_data meson8b_cbus_pinctrl_data = {\n \n struct meson_pinctrl_data meson8b_aobus_pinctrl_data = {\n \t.name\t\t= \"aobus-banks\",\n-\t.pin_base\t= 130,\n+\t.pin_base\t= 0,\n \t.pins\t\t= meson8b_aobus_pins,\n \t.groups\t\t= meson8b_aobus_groups,\n \t.funcs\t\t= meson8b_aobus_functions,\n","prefixes":["5/8"]}