{"id":816143,"url":"http://patchwork.ozlabs.org/api/patches/816143/?format=json","web_url":"http://patchwork.ozlabs.org/project/netdev/patch/1505904778-53217-8-git-send-email-linyunsheng@huawei.com/","project":{"id":7,"url":"http://patchwork.ozlabs.org/api/projects/7/?format=json","name":"Linux network development","link_name":"netdev","list_id":"netdev.vger.kernel.org","list_email":"netdev@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1505904778-53217-8-git-send-email-linyunsheng@huawei.com>","list_archive_url":null,"date":"2017-09-20T10:52:56","name":"[net,7/9] net: hns3: Fix typo error for feild in hclge_tm","commit_ref":null,"pull_url":null,"state":"accepted","archived":true,"hash":"7bffba6e45238f22f354697ca3bc20dc209563df","submitter":{"id":71804,"url":"http://patchwork.ozlabs.org/api/people/71804/?format=json","name":"Yunsheng Lin","email":"linyunsheng@huawei.com"},"delegate":{"id":34,"url":"http://patchwork.ozlabs.org/api/users/34/?format=json","username":"davem","first_name":"David","last_name":"Miller","email":"davem@davemloft.net"},"mbox":"http://patchwork.ozlabs.org/project/netdev/patch/1505904778-53217-8-git-send-email-linyunsheng@huawei.com/mbox/","series":[{"id":4080,"url":"http://patchwork.ozlabs.org/api/series/4080/?format=json","web_url":"http://patchwork.ozlabs.org/project/netdev/list/?series=4080","date":"2017-09-20T10:52:53","name":"TM related bugfixes for the HNS3 Ethernet Driver","version":1,"mbox":"http://patchwork.ozlabs.org/series/4080/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/816143/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/816143/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"patchwork-incoming@ozlabs.org","Delivered-To":"patchwork-incoming@ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xxxTn67s8z9s7c\n\tfor ;\n\tWed, 20 Sep 2017 20:55:09 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752072AbdITKyf (ORCPT );\n\tWed, 20 Sep 2017 06:54:35 -0400","from szxga04-in.huawei.com ([45.249.212.190]:6506 \"EHLO\n\tszxga04-in.huawei.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751920AbdITKx0 (ORCPT\n\t); Wed, 20 Sep 2017 06:53:26 -0400","from 172.30.72.59 (EHLO DGGEMS407-HUB.china.huawei.com)\n\t([172.30.72.59])\n\tby dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued)\n\twith ESMTP id DHP73801; Wed, 20 Sep 2017 18:53:24 +0800 (CST)","from localhost.localdomain (10.67.212.75) by\n\tDGGEMS407-HUB.china.huawei.com (10.3.19.207) with Microsoft SMTP\n\tServer id 14.3.301.0; Wed, 20 Sep 2017 18:53:14 +0800"],"From":"Yunsheng Lin ","To":"","CC":", ,\n\t, ,\n\t, ,\n\t, ,\n\t, ,\n\t, ","Subject":"[PATCH net 7/9] net: hns3: Fix typo error for feild in hclge_tm","Date":"Wed, 20 Sep 2017 18:52:56 +0800","Message-ID":"<1505904778-53217-8-git-send-email-linyunsheng@huawei.com>","X-Mailer":"git-send-email 1.9.1","In-Reply-To":"<1505904778-53217-1-git-send-email-linyunsheng@huawei.com>","References":"<1505904778-53217-1-git-send-email-linyunsheng@huawei.com>","MIME-Version":"1.0","Content-Type":"text/plain","X-Originating-IP":"[10.67.212.75]","X-CFilter-Loop":"Reflected","X-Mirapoint-Virus-RAPID-Raw":"score=unknown(0),\n\trefid=str=0001.0A0B0207.59C248A4.013F, ss=1, re=0.000, recu=0.000,\n\treip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0,\n\tso=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32","X-Mirapoint-Loop-Id":"cc9399df8933bad681eeadaa7a2b0991","Sender":"netdev-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"netdev@vger.kernel.org"},"content":"This patch fixes a typo error for feild, which should be field.\n\nFixes: 848440544b41f (\"net: hns3: Add support of TX Scheduler & Shaper to HNS3 driver\")\nSigned-off-by: Yunsheng Lin \n---\n .../net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c | 20 ++++++++++----------\n .../net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h | 4 ++--\n 2 files changed, 12 insertions(+), 12 deletions(-)","diff":"diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c\nindex c91dbf1..fe659f7 100644\n--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c\n+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c\n@@ -280,11 +280,11 @@ static int hclge_tm_pg_shapping_cfg(struct hclge_dev *hdev,\n \n \tshap_cfg_cmd->pg_id = pg_id;\n \n-\thclge_tm_set_feild(shap_cfg_cmd->pg_shapping_para, IR_B, ir_b);\n-\thclge_tm_set_feild(shap_cfg_cmd->pg_shapping_para, IR_U, ir_u);\n-\thclge_tm_set_feild(shap_cfg_cmd->pg_shapping_para, IR_S, ir_s);\n-\thclge_tm_set_feild(shap_cfg_cmd->pg_shapping_para, BS_B, bs_b);\n-\thclge_tm_set_feild(shap_cfg_cmd->pg_shapping_para, BS_S, bs_s);\n+\thclge_tm_set_field(shap_cfg_cmd->pg_shapping_para, IR_B, ir_b);\n+\thclge_tm_set_field(shap_cfg_cmd->pg_shapping_para, IR_U, ir_u);\n+\thclge_tm_set_field(shap_cfg_cmd->pg_shapping_para, IR_S, ir_s);\n+\thclge_tm_set_field(shap_cfg_cmd->pg_shapping_para, BS_B, bs_b);\n+\thclge_tm_set_field(shap_cfg_cmd->pg_shapping_para, BS_S, bs_s);\n \n \treturn hclge_cmd_send(&hdev->hw, &desc, 1);\n }\n@@ -307,11 +307,11 @@ static int hclge_tm_pri_shapping_cfg(struct hclge_dev *hdev,\n \n \tshap_cfg_cmd->pri_id = pri_id;\n \n-\thclge_tm_set_feild(shap_cfg_cmd->pri_shapping_para, IR_B, ir_b);\n-\thclge_tm_set_feild(shap_cfg_cmd->pri_shapping_para, IR_U, ir_u);\n-\thclge_tm_set_feild(shap_cfg_cmd->pri_shapping_para, IR_S, ir_s);\n-\thclge_tm_set_feild(shap_cfg_cmd->pri_shapping_para, BS_B, bs_b);\n-\thclge_tm_set_feild(shap_cfg_cmd->pri_shapping_para, BS_S, bs_s);\n+\thclge_tm_set_field(shap_cfg_cmd->pri_shapping_para, IR_B, ir_b);\n+\thclge_tm_set_field(shap_cfg_cmd->pri_shapping_para, IR_U, ir_u);\n+\thclge_tm_set_field(shap_cfg_cmd->pri_shapping_para, IR_S, ir_s);\n+\thclge_tm_set_field(shap_cfg_cmd->pri_shapping_para, BS_B, bs_b);\n+\thclge_tm_set_field(shap_cfg_cmd->pri_shapping_para, BS_S, bs_s);\n \n \treturn hclge_cmd_send(&hdev->hw, &desc, 1);\n }\ndiff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h\nindex 7e67337..85158b0 100644\n--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h\n+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h\n@@ -94,10 +94,10 @@ struct hclge_bp_to_qs_map_cmd {\n \tu32 rsvd1;\n };\n \n-#define hclge_tm_set_feild(dest, string, val) \\\n+#define hclge_tm_set_field(dest, string, val) \\\n \t\t\thnae_set_field((dest), (HCLGE_TM_SHAP_##string##_MSK), \\\n \t\t\t\t (HCLGE_TM_SHAP_##string##_LSH), val)\n-#define hclge_tm_get_feild(src, string) \\\n+#define hclge_tm_get_field(src, string) \\\n \t\t\thnae_get_field((src), (HCLGE_TM_SHAP_##string##_MSK), \\\n \t\t\t\t (HCLGE_TM_SHAP_##string##_LSH))\n \n","prefixes":["net","7/9"]}