{"id":816139,"url":"http://patchwork.ozlabs.org/api/patches/816139/?format=json","web_url":"http://patchwork.ozlabs.org/project/netdev/patch/1505904778-53217-10-git-send-email-linyunsheng@huawei.com/","project":{"id":7,"url":"http://patchwork.ozlabs.org/api/projects/7/?format=json","name":"Linux network development","link_name":"netdev","list_id":"netdev.vger.kernel.org","list_email":"netdev@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1505904778-53217-10-git-send-email-linyunsheng@huawei.com>","list_archive_url":null,"date":"2017-09-20T10:52:58","name":"[net,9/9] net: hns3: Fix for pri to tc mapping in TM","commit_ref":null,"pull_url":null,"state":"accepted","archived":true,"hash":"a38ea872a1509a214dbe53c3b29fa05b06f3754b","submitter":{"id":71804,"url":"http://patchwork.ozlabs.org/api/people/71804/?format=json","name":"Yunsheng Lin","email":"linyunsheng@huawei.com"},"delegate":{"id":34,"url":"http://patchwork.ozlabs.org/api/users/34/?format=json","username":"davem","first_name":"David","last_name":"Miller","email":"davem@davemloft.net"},"mbox":"http://patchwork.ozlabs.org/project/netdev/patch/1505904778-53217-10-git-send-email-linyunsheng@huawei.com/mbox/","series":[{"id":4080,"url":"http://patchwork.ozlabs.org/api/series/4080/?format=json","web_url":"http://patchwork.ozlabs.org/project/netdev/list/?series=4080","date":"2017-09-20T10:52:53","name":"TM related bugfixes for the HNS3 Ethernet Driver","version":1,"mbox":"http://patchwork.ozlabs.org/series/4080/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/816139/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/816139/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"patchwork-incoming@ozlabs.org","Delivered-To":"patchwork-incoming@ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xxxSf5y6pz9s7c\n\tfor ;\n\tWed, 20 Sep 2017 20:54:10 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751988AbdITKxk (ORCPT );\n\tWed, 20 Sep 2017 06:53:40 -0400","from szxga04-in.huawei.com ([45.249.212.190]:6510 \"EHLO\n\tszxga04-in.huawei.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751957AbdITKx1 (ORCPT\n\t); Wed, 20 Sep 2017 06:53:27 -0400","from 172.30.72.59 (EHLO DGGEMS407-HUB.china.huawei.com)\n\t([172.30.72.59])\n\tby dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued)\n\twith ESMTP id DHP73809; Wed, 20 Sep 2017 18:53:25 +0800 (CST)","from localhost.localdomain (10.67.212.75) by\n\tDGGEMS407-HUB.china.huawei.com (10.3.19.207) with Microsoft SMTP\n\tServer id 14.3.301.0; Wed, 20 Sep 2017 18:53:15 +0800"],"From":"Yunsheng Lin ","To":"","CC":", ,\n\t, ,\n\t, ,\n\t, ,\n\t, ,\n\t, ","Subject":"[PATCH net 9/9] net: hns3: Fix for pri to tc mapping in TM","Date":"Wed, 20 Sep 2017 18:52:58 +0800","Message-ID":"<1505904778-53217-10-git-send-email-linyunsheng@huawei.com>","X-Mailer":"git-send-email 1.9.1","In-Reply-To":"<1505904778-53217-1-git-send-email-linyunsheng@huawei.com>","References":"<1505904778-53217-1-git-send-email-linyunsheng@huawei.com>","MIME-Version":"1.0","Content-Type":"text/plain","X-Originating-IP":"[10.67.212.75]","X-CFilter-Loop":"Reflected","X-Mirapoint-Virus-RAPID-Raw":"score=unknown(0),\n\trefid=str=0001.0A0B0202.59C248A5.0128, ss=1, re=0.000, recu=0.000,\n\treip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0,\n\tso=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32","X-Mirapoint-Loop-Id":"a4c2c0b5da74a0090b2e95d1447f8030","Sender":"netdev-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"netdev@vger.kernel.org"},"content":"Current mapping between pri and tc is one to one,\nso user can't map multi priorities to the same tc.\nThis patch changes the mapping to many to one.\n\nFixes: 848440544b41f (\"net: hns3: Add support of TX Scheduler & Shaper to HNS3 driver\")\nSigned-off-by: Yunsheng Lin \n---\n drivers/net/ethernet/hisilicon/hns3/hnae3.h | 3 ++-\n drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h | 2 +-\n drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c | 16 +++++++++-------\n 3 files changed, 12 insertions(+), 9 deletions(-)","diff":"diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h\nindex ad685f5..1a01cad 100644\n--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h\n+++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h\n@@ -376,12 +376,12 @@ struct hnae3_ae_algo {\n struct hnae3_tc_info {\n \tu16\ttqp_offset;\t/* TQP offset from base TQP */\n \tu16\ttqp_count;\t/* Total TQPs */\n-\tu8\tup;\t\t/* user priority */\n \tu8\ttc;\t\t/* TC index */\n \tbool\tenable;\t\t/* If this TC is enable or not */\n };\n \n #define HNAE3_MAX_TC\t\t8\n+#define HNAE3_MAX_USER_PRIO\t8\n struct hnae3_knic_private_info {\n \tstruct net_device *netdev; /* Set by KNIC client when init instance */\n \tu16 rss_size;\t\t /* Allocated RSS queues */\n@@ -389,6 +389,7 @@ struct hnae3_knic_private_info {\n \tu16 num_desc;\n \n \tu8 num_tc;\t\t /* Total number of enabled TCs */\n+\tu8 prio_tc[HNAE3_MAX_USER_PRIO]; /* TC indexed by prio */\n \tstruct hnae3_tc_info tc_info[HNAE3_MAX_TC]; /* Idx of array is HW TC */\n \n \tu16 num_tqps;\t\t /* total number of TQPs in this handle */\ndiff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h\nindex 7f8dd12..9fcfd93 100644\n--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h\n+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h\n@@ -176,7 +176,6 @@ struct hclge_pg_info {\n struct hclge_tc_info {\n \tu8 tc_id;\n \tu8 tc_sch_mode;\t\t/* 0: sp; 1: dwrr */\n-\tu8 up;\n \tu8 pgid;\n \tu32 bw_limit;\n };\n@@ -197,6 +196,7 @@ struct hclge_tm_info {\n \tu8 num_tc;\n \tu8 num_pg; /* It must be 1 if vNET-Base schd */\n \tu8 pg_dwrr[HCLGE_PG_NUM];\n+\tu8 prio_tc[HNAE3_MAX_USER_PRIO];\n \tstruct hclge_pg_info pg_info[HCLGE_PG_NUM];\n \tstruct hclge_tc_info tc_info[HNAE3_MAX_TC];\n \tenum hclge_fc_mode fc_mode;\ndiff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c\nindex b7ba7aa..73a75d7 100644\n--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c\n+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c\n@@ -128,9 +128,7 @@ static int hclge_fill_pri_array(struct hclge_dev *hdev, u8 *pri, u8 pri_id)\n {\n \tu8 tc;\n \n-\tfor (tc = 0; tc < hdev->tm_info.num_tc; tc++)\n-\t\tif (hdev->tm_info.tc_info[tc].up == pri_id)\n-\t\t\tbreak;\n+\ttc = hdev->tm_info.prio_tc[pri_id];\n \n \tif (tc >= hdev->tm_info.num_tc)\n \t\treturn -EINVAL;\n@@ -158,7 +156,7 @@ static int hclge_up_to_tc_map(struct hclge_dev *hdev)\n \n \thclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PRI_TO_TC_MAPPING, false);\n \n-\tfor (pri_id = 0; pri_id < hdev->tm_info.num_tc; pri_id++) {\n+\tfor (pri_id = 0; pri_id < HNAE3_MAX_USER_PRIO; pri_id++) {\n \t\tret = hclge_fill_pri_array(hdev, pri, pri_id);\n \t\tif (ret)\n \t\t\treturn ret;\n@@ -405,16 +403,17 @@ static void hclge_tm_vport_tc_info_update(struct hclge_vport *vport)\n \t\t\tkinfo->tc_info[i].tqp_offset = i * kinfo->rss_size;\n \t\t\tkinfo->tc_info[i].tqp_count = kinfo->rss_size;\n \t\t\tkinfo->tc_info[i].tc = i;\n-\t\t\tkinfo->tc_info[i].up = hdev->tm_info.tc_info[i].up;\n \t\t} else {\n \t\t\t/* Set to default queue if TC is disable */\n \t\t\tkinfo->tc_info[i].enable = false;\n \t\t\tkinfo->tc_info[i].tqp_offset = 0;\n \t\t\tkinfo->tc_info[i].tqp_count = 1;\n \t\t\tkinfo->tc_info[i].tc = 0;\n-\t\t\tkinfo->tc_info[i].up = 0;\n \t\t}\n \t}\n+\n+\tmemcpy(kinfo->prio_tc, hdev->tm_info.prio_tc,\n+\t FIELD_SIZEOF(struct hnae3_knic_private_info, prio_tc));\n }\n \n static void hclge_tm_vport_info_update(struct hclge_dev *hdev)\n@@ -436,12 +435,15 @@ static void hclge_tm_tc_info_init(struct hclge_dev *hdev)\n \tfor (i = 0; i < hdev->tm_info.num_tc; i++) {\n \t\thdev->tm_info.tc_info[i].tc_id = i;\n \t\thdev->tm_info.tc_info[i].tc_sch_mode = HCLGE_SCH_MODE_DWRR;\n-\t\thdev->tm_info.tc_info[i].up = i;\n \t\thdev->tm_info.tc_info[i].pgid = 0;\n \t\thdev->tm_info.tc_info[i].bw_limit =\n \t\t\thdev->tm_info.pg_info[0].bw_limit;\n \t}\n \n+\tfor (i = 0; i < HNAE3_MAX_USER_PRIO; i++)\n+\t\thdev->tm_info.prio_tc[i] =\n+\t\t\t(i >= hdev->tm_info.num_tc) ? 0 : i;\n+\n \thdev->flag &= ~HCLGE_FLAG_DCB_ENABLE;\n }\n \n","prefixes":["net","9/9"]}