{"id":816114,"url":"http://patchwork.ozlabs.org/api/patches/816114/?format=json","web_url":"http://patchwork.ozlabs.org/project/devicetree-bindings/patch/3a6338ca5f1513b897cac2facc7c0bf796b8c64f.1505890481.git.sean.wang@mediatek.com/","project":{"id":37,"url":"http://patchwork.ozlabs.org/api/projects/37/?format=json","name":"Devicetree Bindings","link_name":"devicetree-bindings","list_id":"devicetree.vger.kernel.org","list_email":"devicetree@vger.kernel.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<3a6338ca5f1513b897cac2facc7c0bf796b8c64f.1505890481.git.sean.wang@mediatek.com>","list_archive_url":null,"date":"2017-09-20T09:49:25","name":"[1/4] dt-bindings: clock: mediatek: document clk bindings for MediaTek MT7622 SoC","commit_ref":null,"pull_url":null,"state":"not-applicable","archived":true,"hash":"32ba6cb1018fc8cbdcc0ec7ee08de975b2ef7f1a","submitter":{"id":69660,"url":"http://patchwork.ozlabs.org/api/people/69660/?format=json","name":"Sean Wang","email":"sean.wang@mediatek.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/devicetree-bindings/patch/3a6338ca5f1513b897cac2facc7c0bf796b8c64f.1505890481.git.sean.wang@mediatek.com/mbox/","series":[{"id":4067,"url":"http://patchwork.ozlabs.org/api/series/4067/?format=json","web_url":"http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=4067","date":"2017-09-20T09:49:24","name":"add support of clock driver on MediaTek MT7622","version":1,"mbox":"http://patchwork.ozlabs.org/series/4067/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/816114/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/816114/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xxw4216yRz9sPs\n\tfor ;\n\tWed, 20 Sep 2017 19:51:14 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751768AbdITJtl (ORCPT\n\t);\n\tWed, 20 Sep 2017 05:49:41 -0400","from mailgw02.mediatek.com ([210.61.82.184]:27095 \"EHLO\n\tmailgw02.mediatek.com\" rhost-flags-OK-FAIL-OK-FAIL) by\n\tvger.kernel.org with ESMTP id S1751549AbdITJti (ORCPT\n\t); Wed, 20 Sep 2017 05:49:38 -0400","from mtkexhb02.mediatek.inc [(172.21.101.103)] by\n\tmailgw02.mediatek.com (envelope-from )\n\t(mhqrelay.mediatek.com ESMTP with TLS)\n\twith ESMTP id 893343732; Wed, 20 Sep 2017 17:49:33 +0800","from mtkcas09.mediatek.inc (172.21.101.178) by\n\tmtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server\n\t(TLS) id 15.0.1210.3; Wed, 20 Sep 2017 17:49:17 +0800","from mtkswgap22.mediatek.inc (172.21.77.33) by\n\tmtkcas09.mediatek.inc\n\t(172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via\n\tFrontend Transport; Wed, 20 Sep 2017 17:49:50 +0800"],"X-UUID":"cce481586f944c3ca2ec48f210679d03-20170920","From":"","To":", ,\n\t, ,\n\t, ","CC":", ,\n\t, , \n\t, Sean Wang ,\n\tChen Zhong ","Subject":"[PATCH 1/4] dt-bindings: clock: mediatek: document clk bindings for\n\tMediaTek MT7622 SoC","Date":"Wed, 20 Sep 2017 17:49:25 +0800","Message-ID":"<3a6338ca5f1513b897cac2facc7c0bf796b8c64f.1505890481.git.sean.wang@mediatek.com>","X-Mailer":"git-send-email 1.7.9.5","In-Reply-To":"","References":"","MIME-Version":"1.0","Content-Type":"text/plain","X-MTK":"N","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"},"content":"From: Sean Wang \n\nThis patch adds the binding documentation for apmixedsys, ethsys, hifsys,\ninfracfg, pericfg, topckgen and audsys for MT7622.\n\nSigned-off-by: Chen Zhong \nSigned-off-by: Sean Wang \n---\n .../bindings/arm/mediatek/mediatek,apmixedsys.txt | 1 +\n .../bindings/arm/mediatek/mediatek,audsys.txt | 22 ++++++++++++++++++++++\n .../bindings/arm/mediatek/mediatek,ethsys.txt | 1 +\n .../bindings/arm/mediatek/mediatek,hifsys.txt | 1 +\n .../bindings/arm/mediatek/mediatek,infracfg.txt | 1 +\n .../bindings/arm/mediatek/mediatek,pciesys.txt | 22 ++++++++++++++++++++++\n .../bindings/arm/mediatek/mediatek,pericfg.txt | 1 +\n .../bindings/arm/mediatek/mediatek,sgmiisys.txt | 22 ++++++++++++++++++++++\n .../bindings/arm/mediatek/mediatek,ssusbsys.txt | 22 ++++++++++++++++++++++\n .../bindings/arm/mediatek/mediatek,topckgen.txt | 1 +\n 10 files changed, 94 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt\n create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt\n create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt\n create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt","diff":"diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt\nindex cd977db..84669a58 100644\n--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt\n+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt\n@@ -8,6 +8,7 @@ Required Properties:\n - compatible: Should be one of:\n \t- \"mediatek,mt2701-apmixedsys\"\n \t- \"mediatek,mt6797-apmixedsys\"\n+\t- \"mediatek,mt7622-apmixedsys\"\n \t- \"mediatek,mt8135-apmixedsys\"\n \t- \"mediatek,mt8173-apmixedsys\"\n - #clock-cells: Must be 1\ndiff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt\nnew file mode 100644\nindex 0000000..9b8f578\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt\n@@ -0,0 +1,22 @@\n+MediaTek AUDSYS controller\n+============================\n+\n+The MediaTek AUDSYS controller provides various clocks to the system.\n+\n+Required Properties:\n+\n+- compatible: Should be one of:\n+\t- \"mediatek,mt7622-audsys\", \"syscon\"\n+- #clock-cells: Must be 1\n+\n+The AUDSYS controller uses the common clk binding from\n+Documentation/devicetree/bindings/clock/clock-bindings.txt\n+The available clocks are defined in dt-bindings/clock/mt*-clk.h.\n+\n+Example:\n+\n+audsys: audsys@11220000 {\n+\tcompatible = \"mediatek,mt7622-audsys\", \"syscon\";\n+\treg = <0 0x11220000 0 0x1000>;\n+\t#clock-cells = <1>;\n+};\ndiff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt\nindex 768f3a5..7aa3fa1 100644\n--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt\n+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt\n@@ -7,6 +7,7 @@ Required Properties:\n \n - compatible: Should be:\n \t- \"mediatek,mt2701-ethsys\", \"syscon\"\n+\t- \"mediatek,mt7622-ethsys\", \"syscon\"\n - #clock-cells: Must be 1\n \n The ethsys controller uses the common clk binding from\ndiff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt\nindex beed7b5..f5629d6 100644\n--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt\n+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt\n@@ -8,6 +8,7 @@ Required Properties:\n \n - compatible: Should be:\n \t- \"mediatek,mt2701-hifsys\", \"syscon\"\n+\t- \"mediatek,mt7622-hifsys\", \"syscon\"\n - #clock-cells: Must be 1\n \n The hifsys controller uses the common clk binding from\ndiff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt\nindex 58d58e2..56d85b8 100644\n--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt\n+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt\n@@ -9,6 +9,7 @@ Required Properties:\n - compatible: Should be one of:\n \t- \"mediatek,mt2701-infracfg\", \"syscon\"\n \t- \"mediatek,mt6797-infracfg\", \"syscon\"\n+\t- \"mediatek,mt7622-infracfg\", \"syscon\"\n \t- \"mediatek,mt8135-infracfg\", \"syscon\"\n \t- \"mediatek,mt8173-infracfg\", \"syscon\"\n - #clock-cells: Must be 1\ndiff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt\nnew file mode 100644\nindex 0000000..d5d5f12\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt\n@@ -0,0 +1,22 @@\n+MediaTek PCIESYS controller\n+============================\n+\n+The MediaTek PCIESYS controller provides various clocks to the system.\n+\n+Required Properties:\n+\n+- compatible: Should be:\n+\t- \"mediatek,mt7622-pciesys\", \"syscon\"\n+- #clock-cells: Must be 1\n+\n+The PCIESYS controller uses the common clk binding from\n+Documentation/devicetree/bindings/clock/clock-bindings.txt\n+The available clocks are defined in dt-bindings/clock/mt*-clk.h.\n+\n+Example:\n+\n+pciesys: pciesys@1a100800 {\n+\tcompatible = \"mediatek,mt7622-pciesys\", \"syscon\";\n+\treg = <0 0x1a100800 0 0x1000>;\n+\t#clock-cells = <1>;\n+};\ndiff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt\nindex e494366..26c395c 100644\n--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt\n+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt\n@@ -8,6 +8,7 @@ Required Properties:\n \n - compatible: Should be one of:\n \t- \"mediatek,mt2701-pericfg\", \"syscon\"\n+\t- \"mediatek,mt7622-pericfg\", \"syscon\"\n \t- \"mediatek,mt8135-pericfg\", \"syscon\"\n \t- \"mediatek,mt8173-pericfg\", \"syscon\"\n - #clock-cells: Must be 1\ndiff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt\nnew file mode 100644\nindex 0000000..d113b8e\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt\n@@ -0,0 +1,22 @@\n+MediaTek SGMIISYS controller\n+============================\n+\n+The MediaTek SGMIISYS controller provides various clocks to the system.\n+\n+Required Properties:\n+\n+- compatible: Should be:\n+\t- \"mediatek,mt7622-sgmiisys\", \"syscon\"\n+- #clock-cells: Must be 1\n+\n+The SGMIISYS controller uses the common clk binding from\n+Documentation/devicetree/bindings/clock/clock-bindings.txt\n+The available clocks are defined in dt-bindings/clock/mt*-clk.h.\n+\n+Example:\n+\n+sgmiisys: sgmiisys@1b128000 {\n+\tcompatible = \"mediatek,mt7622-sgmiisys\", \"syscon\";\n+\treg = <0 0x1b128000 0 0x1000>;\n+\t#clock-cells = <1>;\n+};\ndiff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt\nnew file mode 100644\nindex 0000000..00760019\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt\n@@ -0,0 +1,22 @@\n+MediaTek SSUSBSYS controller\n+============================\n+\n+The MediaTek SSUSBSYS controller provides various clocks to the system.\n+\n+Required Properties:\n+\n+- compatible: Should be:\n+\t- \"mediatek,mt7622-ssusbsys\", \"syscon\"\n+- #clock-cells: Must be 1\n+\n+The SSUSBSYS controller uses the common clk binding from\n+Documentation/devicetree/bindings/clock/clock-bindings.txt\n+The available clocks are defined in dt-bindings/clock/mt*-clk.h.\n+\n+Example:\n+\n+ssusbsys: ssusbsys@1a000000 {\n+\tcompatible = \"mediatek,mt7622-ssusbsys\", \"syscon\";\n+\treg = <0 0x1a000000 0 0x1000>;\n+\t#clock-cells = <1>;\n+};\ndiff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt\nindex ec93ecb..368b18c 100644\n--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt\n+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt\n@@ -8,6 +8,7 @@ Required Properties:\n - compatible: Should be one of:\n \t- \"mediatek,mt2701-topckgen\"\n \t- \"mediatek,mt6797-topckgen\"\n+\t- \"mediatek,mt7622-topckgen\"\n \t- \"mediatek,mt8135-topckgen\"\n \t- \"mediatek,mt8173-topckgen\"\n - #clock-cells: Must be 1\n","prefixes":["1/4"]}