{"id":816050,"url":"http://patchwork.ozlabs.org/api/patches/816050/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/1505889764-19397-2-git-send-email-mmaddireddy@nvidia.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1505889764-19397-2-git-send-email-mmaddireddy@nvidia.com>","list_archive_url":null,"date":"2017-09-20T06:42:41","name":"[1/4] dt-bindings: pci: tegra: Document Tegra186 PCIe DT","commit_ref":null,"pull_url":null,"state":"superseded","archived":false,"hash":"7af1e64e5ec893b8aae8b0f361da04fa70672ec5","submitter":{"id":72399,"url":"http://patchwork.ozlabs.org/api/people/72399/?format=json","name":"Manikanta Maddireddy","email":"mmaddireddy@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/1505889764-19397-2-git-send-email-mmaddireddy@nvidia.com/mbox/","series":[{"id":4034,"url":"http://patchwork.ozlabs.org/api/series/4034/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=4034","date":"2017-09-20T06:42:41","name":"Add Tegra186 PCIe support","version":1,"mbox":"http://patchwork.ozlabs.org/series/4034/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/816050/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/816050/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xxqx658mLz9s7p\n\tfor ;\n\tWed, 20 Sep 2017 16:44:58 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751618AbdITGoz (ORCPT );\n\tWed, 20 Sep 2017 02:44:55 -0400","from hqemgate15.nvidia.com ([216.228.121.64]:2949 \"EHLO\n\thqemgate15.nvidia.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751284AbdITGoy (ORCPT\n\t); Wed, 20 Sep 2017 02:44:54 -0400","from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by\n\thqemgate15.nvidia.com\n\tid ; Tue, 19 Sep 2017 23:44:21 -0700","from HQMAIL107.nvidia.com ([172.20.161.6])\n\tby hqpgpgate101.nvidia.com (PGP Universal service);\n\tTue, 19 Sep 2017 23:44:23 -0700","from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL107.nvidia.com\n\t(172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1293.2;\n\tWed, 20 Sep 2017 06:43:21 +0000","from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL107.nvidia.com\n\t(172.20.187.13) with Microsoft SMTP Server id 15.0.1293.2 via\n\tFrontend Transport; Wed, 20 Sep 2017 06:43:21 +0000","from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by\n\thqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 5, 8150)\n\tid ; Tue, 19 Sep 2017 23:43:21 -0700"],"X-PGP-Universal":"processed;\n\tby hqpgpgate101.nvidia.com on Tue, 19 Sep 2017 23:44:23 -0700","From":"Manikanta Maddireddy ","To":", , ","CC":", ,\n\tManikanta Maddireddy ","Subject":"[PATCH 1/4] dt-bindings: pci: tegra: Document Tegra186 PCIe DT","Date":"Wed, 20 Sep 2017 12:12:41 +0530","Message-ID":"<1505889764-19397-2-git-send-email-mmaddireddy@nvidia.com>","X-Mailer":"git-send-email 2.1.4","In-Reply-To":"<1505889764-19397-1-git-send-email-mmaddireddy@nvidia.com>","References":"<1505889764-19397-1-git-send-email-mmaddireddy@nvidia.com>","X-NVConfidentiality":"public","MIME-Version":"1.0","Content-Type":"text/plain","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"},"content":"Tegra186 PCIe controller DT properties has couple of differences\nwrt Tegra210 PCIe, rest of the DT properties are same.\n\nSigned-off-by: Manikanta Maddireddy \n---\n .../bindings/pci/nvidia,tegra20-pcie.txt | 134 ++++++++++++++++++++-\n 1 file changed, 130 insertions(+), 4 deletions(-)","diff":"diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt\nindex 982a74ea6df9..753b67327373 100644\n--- a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt\n+++ b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt\n@@ -1,10 +1,15 @@\n NVIDIA Tegra PCIe controller\n \n Required properties:\n-- compatible: For Tegra20, must contain \"nvidia,tegra20-pcie\". For Tegra30,\n- \"nvidia,tegra30-pcie\". For Tegra124, must contain \"nvidia,tegra124-pcie\".\n- Otherwise, must contain \"nvidia,-pcie\", plus one of the above, where\n- is tegra132 or tegra210.\n+- compatible: Must be:\n+ - \"nvidia,tegra20-pcie\": for Tegra20\n+ - \"nvidia,tegra30-pcie\": for Tegra30\n+ - \"nvidia,tegra124-pcie\": for Tegra124 and Tegra132\n+ - \"nvidia,tegra210-pcie\": for Tegra210\n+ - \"nvidia,tegra186-pcie\": for Tegra186\n+- power-domains: To ungate power partition by BPMP powergate driver. Must\n+contain BPMP phandle and PCIe power partition ID. This is required only\n+for Tegra186.\n - device_type: Must be \"pci\"\n - reg: A list of physical base address and length for each set of controller\n registers. Must contain an entry for each entry in the reg-names property.\n@@ -124,6 +129,16 @@ Power supplies for Tegra210:\n - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must\n supply 1.8 V.\n \n+Power supplies for Tegra186:\n+- Required:\n+ - dvdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.\n+ - hvdd-pex-pll-supply: High-voltage supply for PLLE (shared with USB3). Must\n+ supply 1.8 V.\n+ - hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks.\n+ Must supply 1.8 V.\n+ - vddio-pexctl-aud-supply: Power supply for PCIe side band signals. Must\n+ supply 1.8 V.\n+\n Root ports are defined as subnodes of the PCIe controller node.\n \n Required properties:\n@@ -546,3 +561,114 @@ Board DTS:\n \t\t\tstatus = \"okay\";\n \t\t};\n \t};\n+\n+Tegra186:\n+---------\n+\n+SoC DTSI:\n+\n+\tpcie@10003000 {\n+\t\tcompatible = \"nvidia,tegra186-pcie\";\n+\t\tpower-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;\n+\t\tdevice_type = \"pci\";\n+\t\treg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */\n+\t\t 0x0 0x10003800 0x0 0x00000800 /* AFI registers */\n+\t\t 0x0 0x40000000 0x0 0x10000000>; /* configuration space */\n+\t\treg-names = \"pads\", \"afi\", \"cs\";\n+\n+\t\tinterrupts = , /* controller interrupt */\n+\t\t\t ; /* MSI interrupt */\n+\t\tinterrupt-names = \"intr\", \"msi\";\n+\n+\t\t#interrupt-cells = <1>;\n+\t\tinterrupt-map-mask = <0 0 0 0>;\n+\t\tinterrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;\n+\n+\t\tbus-range = <0x00 0xff>;\n+\t\t#address-cells = <3>;\n+\t\t#size-cells = <2>;\n+\n+\t\tranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */\n+\t\t\t 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */\n+\t\t\t 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */\n+\t\t\t 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */\n+\t\t\t 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */\n+\t\t\t 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */\n+\n+\t\tclocks = <&bpmp TEGRA186_CLK_AFI>,\n+\t\t\t <&bpmp TEGRA186_CLK_PCIE>,\n+\t\t\t <&bpmp TEGRA186_CLK_PLLE>;\n+\t\tclock-names = \"afi\", \"pex\", \"pll_e\";\n+\n+\t\tresets = <&bpmp TEGRA186_RESET_AFI>,\n+\t\t\t <&bpmp TEGRA186_RESET_PCIE>,\n+\t\t\t <&bpmp TEGRA186_RESET_PCIEXCLK>;\n+\t\treset-names = \"afi\", \"pex\", \"pcie_x\";\n+\n+\t\tstatus = \"disabled\";\n+\n+\t\tpci@1,0 {\n+\t\t\tdevice_type = \"pci\";\n+\t\t\tassigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;\n+\t\t\treg = <0x000800 0 0 0 0>;\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\t#address-cells = <3>;\n+\t\t\t#size-cells = <2>;\n+\t\t\tranges;\n+\n+\t\t\tnvidia,num-lanes = <2>;\n+\t\t};\n+\n+\t\tpci@2,0 {\n+\t\t\tdevice_type = \"pci\";\n+\t\t\tassigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;\n+\t\t\treg = <0x001000 0 0 0 0>;\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\t#address-cells = <3>;\n+\t\t\t#size-cells = <2>;\n+\t\t\tranges;\n+\n+\t\t\tnvidia,num-lanes = <1>;\n+\t\t};\n+\n+\t\tpci@3,0 {\n+\t\t\tdevice_type = \"pci\";\n+\t\t\tassigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;\n+\t\t\treg = <0x001800 0 0 0 0>;\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\t#address-cells = <3>;\n+\t\t\t#size-cells = <2>;\n+\t\t\tranges;\n+\n+\t\t\tnvidia,num-lanes = <1>;\n+\t\t};\n+\t};\n+\n+Board DTS:\n+\n+\tpcie@10003000 {\n+\t\tstatus = \"okay\";\n+\n+\t\tdvdd-pex-supply = <&vdd_pex>;\n+\t\thvdd-pex-pll-supply = <&vdd_1v8>;\n+\t\thvdd-pex-supply = <&vdd_1v8>;\n+\t\tvddio-pexctl-aud-supply = <&vdd_1v8>;\n+\n+\t\tpci@1,0 {\n+\t\t\tnvidia,num-lanes = <4>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\n+\t\tpci@2,0 {\n+\t\t\tnvidia,num-lanes = <0>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tpci@3,0 {\n+\t\t\tnvidia,num-lanes = <1>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n","prefixes":["1/4"]}