{"id":816041,"url":"http://patchwork.ozlabs.org/api/patches/816041/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1505888909-98816-5-git-send-email-david.wu@rock-chips.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1505888909-98816-5-git-send-email-david.wu@rock-chips.com>","list_archive_url":null,"date":"2017-09-20T06:28:19","name":"[U-Boot,v3,04/14] rockchip: clk: Add SARADC clock support for rk3288","commit_ref":null,"pull_url":null,"state":"accepted","archived":false,"hash":"f623b7885a86147e071e9ab63b7d3ddd808c5072","submitter":{"id":68083,"url":"http://patchwork.ozlabs.org/api/people/68083/?format=json","name":"David Wu","email":"david.wu@rock-chips.com"},"delegate":{"id":69486,"url":"http://patchwork.ozlabs.org/api/users/69486/?format=json","username":"ptomsich","first_name":"Philipp","last_name":"Tomsich","email":"philipp.tomsich@theobroma-systems.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1505888909-98816-5-git-send-email-david.wu@rock-chips.com/mbox/","series":[{"id":4030,"url":"http://patchwork.ozlabs.org/api/series/4030/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=4030","date":"2017-09-20T06:28:15","name":"Add rockchip SARADC support","version":3,"mbox":"http://patchwork.ozlabs.org/series/4030/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/816041/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/816041/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xxqdz6Jlzz9s7h\n\tfor ;\n\tWed, 20 Sep 2017 16:31:51 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 9AFCCC21DCA; Wed, 20 Sep 2017 06:31:14 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id DFD4CC21D80;\n\tWed, 20 Sep 2017 06:30:31 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid E215FC21DA9; Wed, 20 Sep 2017 06:30:14 +0000 (UTC)","from lucky1.263xmail.com (lucky1.263xmail.com [211.157.147.134])\n\tby lists.denx.de (Postfix) with ESMTPS id 58F80C21DE5\n\tfor ; Wed, 20 Sep 2017 06:30:13 +0000 (UTC)","from david.wu?rock-chips.com (unknown [192.168.167.224])\n\tby lucky1.263xmail.com (Postfix) with ESMTP id EB93B1388;\n\tWed, 20 Sep 2017 14:30:09 +0800 (CST)","from localhost.localdomain (localhost [127.0.0.1])\n\tby smtp.263.net (Postfix) with ESMTPA id 63E62369;\n\tWed, 20 Sep 2017 14:30:08 +0800 (CST)","from unknown (unknown [58.22.7.114])\n\tby smtp.263.net (Postfix) whith SMTP id 13379TYZ5KO;\n\tWed, 20 Sep 2017 14:30:09 +0800 (CST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=0.6 required=5.0 tests=RCVD_IN_MSPIKE_BL,\n\tRCVD_IN_MSPIKE_L4,RCVD_IN_SORBS_WEB autolearn=no autolearn_force=no\n\tversion=3.4.0","X-263anti-spam":"KSV:0;","X-MAIL-GRAY":"1","X-MAIL-DELIVERY":"0","X-KSVirus-check":"0","X-ABS-CHECKED":"4","X-RL-SENDER":"david.wu@rock-chips.com","X-FST-TO":"philipp.tomsich@theobroma-systems.com","X-SENDER-IP":"58.22.7.114","X-LOGIN-NAME":"david.wu@rock-chips.com","X-UNIQUE-TAG":"","X-ATTACHMENT-NUM":"0","X-SENDER":"wdc@rock-chips.com","X-DNS-TYPE":"0","From":"David Wu ","To":"philipp.tomsich@theobroma-systems.com,\n\tsjg@chromium.org","Date":"Wed, 20 Sep 2017 14:28:19 +0800","Message-Id":"<1505888909-98816-5-git-send-email-david.wu@rock-chips.com>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1505888909-98816-1-git-send-email-david.wu@rock-chips.com>","References":"<1505888909-98816-1-git-send-email-david.wu@rock-chips.com>","Cc":"huangtao@rock-chips.com, zhangqing@rock-chips.com, u-boot@lists.denx.de, \n\tdavid.wu@rock-chips.com, andy.yan@rock-chips.com, chenjh@rock-chips.com","Subject":"[U-Boot] [PATCH v3 04/14] rockchip: clk: Add SARADC clock support\n\tfor rk3288","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).\nSARADC integer divider control register is 8-bits width.\n\nSigned-off-by: David Wu \nReviewed-by: Philipp Tomsich \nAcked-by: Philipp Tomsich \n---\n\nChanges in v3: None\nChanges in v2:\n- Use bitfield_extract\n- Use GENMASK\n\n drivers/clk/rockchip/clk_rk3288.c | 41 +++++++++++++++++++++++++++++++++++++++\n 1 file changed, 41 insertions(+)","diff":"diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c\nindex 478195b..a133810 100644\n--- a/drivers/clk/rockchip/clk_rk3288.c\n+++ b/drivers/clk/rockchip/clk_rk3288.c\n@@ -5,6 +5,7 @@\n */\n \n #include \n+#include \n #include \n #include \n #include \n@@ -111,6 +112,15 @@ enum {\n \tPERI_ACLK_DIV_SHIFT\t= 0,\n \tPERI_ACLK_DIV_MASK\t= 0x1f << PERI_ACLK_DIV_SHIFT,\n \n+\t/*\n+\t * CLKSEL24\n+\t * saradc_div_con:\n+\t * clk_saradc=24MHz/(saradc_div_con+1)\n+\t */\n+\tCLK_SARADC_DIV_CON_SHIFT\t= 8,\n+\tCLK_SARADC_DIV_CON_MASK\t\t= GENMASK(15, 8),\n+\tCLK_SARADC_DIV_CON_WIDTH\t= 8,\n+\n \tSOCSTS_DPLL_LOCK\t= 1 << 5,\n \tSOCSTS_APLL_LOCK\t= 1 << 6,\n \tSOCSTS_CPLL_LOCK\t= 1 << 7,\n@@ -634,6 +644,31 @@ static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate,\n \treturn rockchip_spi_get_clk(cru, gclk_rate, periph);\n }\n \n+static ulong rockchip_saradc_get_clk(struct rk3288_cru *cru)\n+{\n+\tu32 div, val;\n+\n+\tval = readl(&cru->cru_clksel_con[24]);\n+\tdiv = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,\n+\t\t\t CLK_SARADC_DIV_CON_WIDTH);\n+\n+\treturn DIV_TO_RATE(OSC_HZ, div);\n+}\n+\n+static ulong rockchip_saradc_set_clk(struct rk3288_cru *cru, uint hz)\n+{\n+\tint src_clk_div;\n+\n+\tsrc_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;\n+\tassert(src_clk_div < 128);\n+\n+\trk_clrsetreg(&cru->cru_clksel_con[24],\n+\t\t CLK_SARADC_DIV_CON_MASK,\n+\t\t src_clk_div << CLK_SARADC_DIV_CON_SHIFT);\n+\n+\treturn rockchip_saradc_get_clk(cru);\n+}\n+\n static ulong rk3288_clk_get_rate(struct clk *clk)\n {\n \tstruct rk3288_clk_priv *priv = dev_get_priv(clk->dev);\n@@ -666,6 +701,9 @@ static ulong rk3288_clk_get_rate(struct clk *clk)\n \t\treturn gclk_rate;\n \tcase PCLK_PWM:\n \t\treturn PD_BUS_PCLK_HZ;\n+\tcase SCLK_SARADC:\n+\t\tnew_rate = rockchip_saradc_get_clk(priv->cru);\n+\t\tbreak;\n \tdefault:\n \t\treturn -ENOENT;\n \t}\n@@ -756,6 +794,9 @@ static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate)\n \t\tnew_rate = rate;\n \t\tbreak;\n #endif\n+\tcase SCLK_SARADC:\n+\t\tnew_rate = rockchip_saradc_set_clk(priv->cru, rate);\n+\t\tbreak;\n \tdefault:\n \t\treturn -ENOENT;\n \t}\n","prefixes":["U-Boot","v3","04/14"]}