{"id":816034,"url":"http://patchwork.ozlabs.org/api/patches/816034/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1505888401-10130-2-git-send-email-mark.cave-ayland@ilande.co.uk/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1505888401-10130-2-git-send-email-mark.cave-ayland@ilande.co.uk>","list_archive_url":null,"date":"2017-09-20T06:20:00","name":"[1/2] ppc/ide/macio: Add missing registers","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"835bccae84488a4e7ce32e357cd9c90dfba10f97","submitter":{"id":12451,"url":"http://patchwork.ozlabs.org/api/people/12451/?format=json","name":"Mark Cave-Ayland","email":"mark.cave-ayland@ilande.co.uk"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1505888401-10130-2-git-send-email-mark.cave-ayland@ilande.co.uk/mbox/","series":[{"id":4028,"url":"http://patchwork.ozlabs.org/api/series/4028/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=4028","date":"2017-09-20T06:20:01","name":"macio patches","version":1,"mbox":"http://patchwork.ozlabs.org/series/4028/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/816034/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/816034/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xxqPj4qp4z9s7h\n\tfor ;\n\tWed, 20 Sep 2017 16:21:13 +1000 (AEST)","from localhost ([::1]:46921 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1duYNj-0003Ol-5I\n\tfor incoming@patchwork.ozlabs.org; Wed, 20 Sep 2017 02:21:11 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:34144)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1duYMu-0003LW-Ob\n\tfor qemu-devel@nongnu.org; Wed, 20 Sep 2017 02:20:22 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1duYMr-0006Vi-Kf\n\tfor qemu-devel@nongnu.org; Wed, 20 Sep 2017 02:20:20 -0400","from chuckie.co.uk ([82.165.15.123]:54653\n\thelo=s16892447.onlinehome-server.info)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1duYMr-0006QI-DR; Wed, 20 Sep 2017 02:20:17 -0400","from host109-151-159-252.range109-151.btcentralplus.com\n\t([109.151.159.252] helo=kentang.home)\n\tby s16892447.onlinehome-server.info with esmtpsa\n\t(TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76)\n\t(envelope-from )\n\tid 1duYMq-0005qd-PJ; Wed, 20 Sep 2017 07:20:18 +0100"],"From":"Mark Cave-Ayland ","To":"qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au","Date":"Wed, 20 Sep 2017 07:20:00 +0100","Message-Id":"<1505888401-10130-2-git-send-email-mark.cave-ayland@ilande.co.uk>","X-Mailer":"git-send-email 1.7.10.4","In-Reply-To":"<1505888401-10130-1-git-send-email-mark.cave-ayland@ilande.co.uk>","References":"<1505888401-10130-1-git-send-email-mark.cave-ayland@ilande.co.uk>","X-SA-Exim-Connect-IP":"109.151.159.252","X-SA-Exim-Mail-From":"mark.cave-ayland@ilande.co.uk","X-SA-Exim-Version":"4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000)","X-SA-Exim-Scanned":"Yes (on s16892447.onlinehome-server.info)","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 3.x [fuzzy]","X-Received-From":"82.165.15.123","Subject":"[Qemu-devel] [PATCH 1/2] ppc/ide/macio: Add missing registers","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"From: Benjamin Herrenschmidt \n\nThe timing register exists on all variants of MacIO IDE, we just\nstore and return its value.\n\nThe interrupts register only exists on KeyLargo but it doesn't\nhurt to have it. The lack of this register causes MacOS X to\nhangs under some circumstances.\n\nBoth are 32-bit only. The HW might support smaller access sizes\nbut no known OS uses them.\n\nBecause the core IDE subsystem doesn't provide us with a way\nto query the main (level) interrupt state, nor do we have a way\nto know that DBDMA issued a (edge) interrupt, we reflect both\nthrough a private pair of qirq's in order to maintain the\nregister state.\n\nSigned-off-by: Benjamin Herrenschmidt \n---\n hw/ide/macio.c | 44 +++++++++++++++++++++++++++++++++++++++++---\n hw/ppc/mac.h | 6 +++++-\n 2 files changed, 46 insertions(+), 4 deletions(-)","diff":"diff --git a/hw/ide/macio.c b/hw/ide/macio.c\nindex 9742c00..db5db39 100644\n--- a/hw/ide/macio.c\n+++ b/hw/ide/macio.c\n@@ -331,6 +331,12 @@ static void pmac_ide_writel (void *opaque,\n val = bswap32(val);\n if (addr == 0) {\n ide_data_writel(&d->bus, 0, val);\n+ } else if (addr == 0x20) {\n+ d->timing_reg = val;\n+ } else if (addr == 0x30) {\n+ if (val & 0x80000000u) {\n+ d->irq_reg &= 0x7fffffff;\n+ }\n }\n }\n \n@@ -342,6 +348,17 @@ static uint32_t pmac_ide_readl (void *opaque,hwaddr addr)\n addr = (addr & 0xFFF) >> 4;\n if (addr == 0) {\n retval = ide_data_readl(&d->bus, 0);\n+ } else if (addr == 0x20) {\n+ retval = d->timing_reg;\n+ } else if (addr == 0x30) {\n+ /* This is an interrupt state register that only exists\n+ * in the KeyLargo and later variants. Bit 0x8000_0000\n+ * latches the DMA interrupt and has to be written to\n+ * clear. Bit 0x4000_0000 is an image of the disk\n+ * interrupt. MacOS X relies on this and will hang if\n+ * we don't provide at least the disk interrupt\n+ */\n+ retval = d->irq_reg;\n } else {\n retval = 0xFFFFFFFF;\n }\n@@ -426,13 +443,32 @@ static void macio_ide_realizefn(DeviceState *dev, Error **errp)\n {\n MACIOIDEState *s = MACIO_IDE(dev);\n \n- ide_init2(&s->bus, s->irq);\n+ ide_init2(&s->bus, s->ide_irq);\n \n /* Register DMA callbacks */\n s->dma.ops = &dbdma_ops;\n s->bus.dma = &s->dma;\n }\n \n+static void pmac_ide_irq(void *opaque, int n, int level)\n+{\n+ MACIOIDEState *s = opaque;\n+ uint32_t mask = 0x80000000u >> n;\n+\n+ /* We need to reflect the IRQ state in the irq register */\n+ if (level) {\n+ s->irq_reg |= mask;\n+ } else {\n+ s->irq_reg &= ~mask;\n+ }\n+\n+ if (n) {\n+ qemu_set_irq(s->real_ide_irq, level);\n+ } else {\n+ qemu_set_irq(s->real_dma_irq, level);\n+ }\n+}\n+\n static void macio_ide_initfn(Object *obj)\n {\n SysBusDevice *d = SYS_BUS_DEVICE(obj);\n@@ -441,8 +477,10 @@ static void macio_ide_initfn(Object *obj)\n ide_bus_new(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2);\n memory_region_init_io(&s->mem, obj, &pmac_ide_ops, s, \"pmac-ide\", 0x1000);\n sysbus_init_mmio(d, &s->mem);\n- sysbus_init_irq(d, &s->irq);\n- sysbus_init_irq(d, &s->dma_irq);\n+ sysbus_init_irq(d, &s->real_ide_irq);\n+ sysbus_init_irq(d, &s->real_dma_irq);\n+ s->dma_irq = qemu_allocate_irq(pmac_ide_irq, s, 0);\n+ s->ide_irq = qemu_allocate_irq(pmac_ide_irq, s, 1);\n }\n \n static void macio_ide_class_init(ObjectClass *oc, void *data)\ndiff --git a/hw/ppc/mac.h b/hw/ppc/mac.h\nindex 20cbddb..300fc8a 100644\n--- a/hw/ppc/mac.h\n+++ b/hw/ppc/mac.h\n@@ -132,7 +132,9 @@ typedef struct MACIOIDEState {\n SysBusDevice parent_obj;\n /*< public >*/\n \n- qemu_irq irq;\n+ qemu_irq real_ide_irq;\n+ qemu_irq real_dma_irq;\n+ qemu_irq ide_irq;\n qemu_irq dma_irq;\n \n MemoryRegion mem;\n@@ -140,6 +142,8 @@ typedef struct MACIOIDEState {\n IDEDMA dma;\n void *dbdma;\n bool dma_active;\n+ uint32_t timing_reg;\n+ uint32_t irq_reg;\n } MACIOIDEState;\n \n void macio_ide_init_drives(MACIOIDEState *ide, DriveInfo **hd_table);\n","prefixes":["1/2"]}