{"id":816033,"url":"http://patchwork.ozlabs.org/api/patches/816033/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1505888401-10130-3-git-send-email-mark.cave-ayland@ilande.co.uk/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1505888401-10130-3-git-send-email-mark.cave-ayland@ilande.co.uk>","list_archive_url":null,"date":"2017-09-20T06:20:01","name":"[2/2] macio: convert pmac_ide_ops from old_mmio","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"1404f9eee3d67fe7259fb289806165aa35cab5ab","submitter":{"id":12451,"url":"http://patchwork.ozlabs.org/api/people/12451/?format=json","name":"Mark Cave-Ayland","email":"mark.cave-ayland@ilande.co.uk"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1505888401-10130-3-git-send-email-mark.cave-ayland@ilande.co.uk/mbox/","series":[{"id":4028,"url":"http://patchwork.ozlabs.org/api/series/4028/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=4028","date":"2017-09-20T06:20:01","name":"macio patches","version":1,"mbox":"http://patchwork.ozlabs.org/series/4028/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/816033/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/816033/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xxqPd3mPSz9s7h\n\tfor ;\n\tWed, 20 Sep 2017 16:21:09 +1000 (AEST)","from localhost ([::1]:46920 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1duYNf-0003OH-Gd\n\tfor incoming@patchwork.ozlabs.org; Wed, 20 Sep 2017 02:21:07 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:34142)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1duYMu-0003LU-NT\n\tfor qemu-devel@nongnu.org; Wed, 20 Sep 2017 02:20:22 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1duYMr-0006XP-Uv\n\tfor qemu-devel@nongnu.org; Wed, 20 Sep 2017 02:20:20 -0400","from chuckie.co.uk ([82.165.15.123]:54656\n\thelo=s16892447.onlinehome-server.info)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1duYMr-0006S0-Lz; Wed, 20 Sep 2017 02:20:17 -0400","from host109-151-159-252.range109-151.btcentralplus.com\n\t([109.151.159.252] helo=kentang.home)\n\tby s16892447.onlinehome-server.info with esmtpsa\n\t(TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76)\n\t(envelope-from )\n\tid 1duYMs-0005qd-A0; Wed, 20 Sep 2017 07:20:19 +0100"],"From":"Mark Cave-Ayland ","To":"qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au","Date":"Wed, 20 Sep 2017 07:20:01 +0100","Message-Id":"<1505888401-10130-3-git-send-email-mark.cave-ayland@ilande.co.uk>","X-Mailer":"git-send-email 1.7.10.4","In-Reply-To":"<1505888401-10130-1-git-send-email-mark.cave-ayland@ilande.co.uk>","References":"<1505888401-10130-1-git-send-email-mark.cave-ayland@ilande.co.uk>","X-SA-Exim-Connect-IP":"109.151.159.252","X-SA-Exim-Mail-From":"mark.cave-ayland@ilande.co.uk","X-SA-Exim-Version":"4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000)","X-SA-Exim-Scanned":"Yes (on s16892447.onlinehome-server.info)","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 3.x [fuzzy]","X-Received-From":"82.165.15.123","Subject":"[Qemu-devel] [PATCH 2/2] macio: convert pmac_ide_ops from old_mmio","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"Signed-off-by: Mark Cave-Ayland \n---\n hw/ide/macio.c | 181 +++++++++++++++++++++++---------------------------------\n 1 file changed, 75 insertions(+), 106 deletions(-)","diff":"diff --git a/hw/ide/macio.c b/hw/ide/macio.c\nindex db5db39..18ae952 100644\n--- a/hw/ide/macio.c\n+++ b/hw/ide/macio.c\n@@ -255,131 +255,100 @@ static void pmac_ide_flush(DBDMA_io *io)\n }\n \n /* PowerMac IDE memory IO */\n-static void pmac_ide_writeb (void *opaque,\n- hwaddr addr, uint32_t val)\n+static uint64_t pmac_ide_read(void *opaque, hwaddr addr, unsigned size)\n {\n MACIOIDEState *d = opaque;\n-\n- addr = (addr & 0xFFF) >> 4;\n- switch (addr) {\n- case 1 ... 7:\n- ide_ioport_write(&d->bus, addr, val);\n- break;\n- case 8:\n- case 22:\n- ide_cmd_write(&d->bus, 0, val);\n+ uint64_t retval = 0xffffffff;\n+ int reg = addr >> 4;\n+\n+ switch (reg) {\n+ case 0x0:\n+ if (size == 2) {\n+ retval = ide_data_readw(&d->bus, 0);\n+ } else if (size == 4) {\n+ retval = ide_data_readl(&d->bus, 0);\n+ }\n break;\n- default:\n+ case 0x1 ... 0x7:\n+ if (size == 1) {\n+ retval = ide_ioport_read(&d->bus, reg);\n+ }\n break;\n- }\n-}\n-\n-static uint32_t pmac_ide_readb (void *opaque,hwaddr addr)\n-{\n- uint8_t retval;\n- MACIOIDEState *d = opaque;\n-\n- addr = (addr & 0xFFF) >> 4;\n- switch (addr) {\n- case 1 ... 7:\n- retval = ide_ioport_read(&d->bus, addr);\n+ case 0x8:\n+ case 0x16:\n+ if (size == 1) {\n+ retval = ide_status_read(&d->bus, 0);\n+ }\n break;\n- case 8:\n- case 22:\n- retval = ide_status_read(&d->bus, 0);\n+ case 0x20:\n+ if (size == 4) {\n+ retval = d->timing_reg;\n+ }\n break;\n- default:\n- retval = 0xFF;\n+ case 0x30:\n+ /* This is an interrupt state register that only exists\n+ * in the KeyLargo and later variants. Bit 0x8000_0000\n+ * latches the DMA interrupt and has to be written to\n+ * clear. Bit 0x4000_0000 is an image of the disk\n+ * interrupt. MacOS X relies on this and will hang if\n+ * we don't provide at least the disk interrupt\n+ */\n+ if (size == 4) {\n+ retval = d->irq_reg;\n+ }\n break;\n }\n- return retval;\n-}\n \n-static void pmac_ide_writew (void *opaque,\n- hwaddr addr, uint32_t val)\n-{\n- MACIOIDEState *d = opaque;\n-\n- addr = (addr & 0xFFF) >> 4;\n- val = bswap16(val);\n- if (addr == 0) {\n- ide_data_writew(&d->bus, 0, val);\n- }\n-}\n-\n-static uint32_t pmac_ide_readw (void *opaque,hwaddr addr)\n-{\n- uint16_t retval;\n- MACIOIDEState *d = opaque;\n-\n- addr = (addr & 0xFFF) >> 4;\n- if (addr == 0) {\n- retval = ide_data_readw(&d->bus, 0);\n- } else {\n- retval = 0xFFFF;\n- }\n- retval = bswap16(retval);\n return retval;\n }\n \n-static void pmac_ide_writel (void *opaque,\n- hwaddr addr, uint32_t val)\n-{\n- MACIOIDEState *d = opaque;\n \n- addr = (addr & 0xFFF) >> 4;\n- val = bswap32(val);\n- if (addr == 0) {\n- ide_data_writel(&d->bus, 0, val);\n- } else if (addr == 0x20) {\n- d->timing_reg = val;\n- } else if (addr == 0x30) {\n- if (val & 0x80000000u) {\n- d->irq_reg &= 0x7fffffff;\n- }\n- }\n-}\n-\n-static uint32_t pmac_ide_readl (void *opaque,hwaddr addr)\n+static void pmac_ide_write(void *opaque, hwaddr addr, uint64_t val,\n+ unsigned size)\n {\n- uint32_t retval;\n MACIOIDEState *d = opaque;\n-\n- addr = (addr & 0xFFF) >> 4;\n- if (addr == 0) {\n- retval = ide_data_readl(&d->bus, 0);\n- } else if (addr == 0x20) {\n- retval = d->timing_reg;\n- } else if (addr == 0x30) {\n- /* This is an interrupt state register that only exists\n- * in the KeyLargo and later variants. Bit 0x8000_0000\n- * latches the DMA interrupt and has to be written to\n- * clear. Bit 0x4000_0000 is an image of the disk\n- * interrupt. MacOS X relies on this and will hang if\n- * we don't provide at least the disk interrupt\n- */\n- retval = d->irq_reg;\n- } else {\n- retval = 0xFFFFFFFF;\n+ int reg = addr >> 4;\n+\n+ switch (reg) {\n+ case 0x0:\n+ if (size == 2) {\n+ ide_data_writew(&d->bus, 0, val);\n+ } else if (size == 4) {\n+ ide_data_writel(&d->bus, 0, val);\n+ }\n+ break;\n+ case 0x1 ... 0x7:\n+ if (size == 1) {\n+ ide_ioport_write(&d->bus, reg, val);\n+ }\n+ break;\n+ case 0x8:\n+ case 0x16:\n+ if (size == 1) {\n+ ide_cmd_write(&d->bus, 0, val);\n+ }\n+ break;\n+ case 0x20:\n+ if (size == 4) {\n+ d->timing_reg = val;\n+ }\n+ break;\n+ case 0x30:\n+ if (size == 4) {\n+ if (val & 0x80000000u) {\n+ d->irq_reg &= 0x7fffffff;\n+ }\n+ }\n+ break;\n }\n- retval = bswap32(retval);\n- return retval;\n }\n \n static const MemoryRegionOps pmac_ide_ops = {\n- .old_mmio = {\n- .write = {\n- pmac_ide_writeb,\n- pmac_ide_writew,\n- pmac_ide_writel,\n- },\n- .read = {\n- pmac_ide_readb,\n- pmac_ide_readw,\n- pmac_ide_readl,\n- },\n- },\n- .endianness = DEVICE_NATIVE_ENDIAN,\n+ .read = pmac_ide_read,\n+ .write = pmac_ide_write,\n+ .valid.min_access_size = 1,\n+ .valid.max_access_size = 4,\n+ .endianness = DEVICE_LITTLE_ENDIAN,\n };\n \n static const VMStateDescription vmstate_pmac = {\n","prefixes":["2/2"]}