{"id":815785,"url":"http://patchwork.ozlabs.org/api/patches/815785/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1505846281-19020-6-git-send-email-jteki@openedev.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1505846281-19020-6-git-send-email-jteki@openedev.com>","list_archive_url":null,"date":"2017-09-19T18:38:00","name":"[U-Boot,5/6] i.MX6Q: icore: Add SPL_OF_CONTROL support","commit_ref":null,"pull_url":null,"state":"superseded","archived":false,"hash":"cb4147c296155f2b2954756cb6724dbdb37383f9","submitter":{"id":20045,"url":"http://patchwork.ozlabs.org/api/people/20045/?format=json","name":"Jagan Teki","email":"jagannadh.teki@gmail.com"},"delegate":{"id":1693,"url":"http://patchwork.ozlabs.org/api/users/1693/?format=json","username":"sbabic","first_name":"Stefano","last_name":"Babic","email":"sbabic@denx.de"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1505846281-19020-6-git-send-email-jteki@openedev.com/mbox/","series":[{"id":3946,"url":"http://patchwork.ozlabs.org/api/series/3946/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=3946","date":"2017-09-19T18:37:55","name":"i.MX6Q: Add SPL_OF_CONTROL support","version":1,"mbox":"http://patchwork.ozlabs.org/series/3946/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/815785/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/815785/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) 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+0530","Message-Id":"<1505846281-19020-6-git-send-email-jteki@openedev.com>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1505846281-19020-1-git-send-email-jteki@openedev.com>","References":"<1505846281-19020-1-git-send-email-jteki@openedev.com>","Cc":"Fabio Estevam , u-boot@lists.denx.de","Subject":"[U-Boot] [PATCH 5/6] i.MX6Q: icore: Add SPL_OF_CONTROL support","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"From: Jagan Teki \n\nAdd OF_CONTROL support for SPL code.\n\nSigned-off-by: Jagan Teki \n---\n arch/arm/dts/imx6qdl-icore-rqs.dtsi | 2 +\n arch/arm/dts/imx6qdl-icore.dtsi | 2 +\n arch/arm/dts/imx6qdl.dtsi | 5 ++\n arch/arm/mach-imx/mx6/Kconfig | 8 +++\n board/engicam/icorem6/icorem6.c | 75 -----------------------\n board/engicam/icorem6_rqs/icorem6_rqs.c | 102 --------------------------------\n configs/imx6qdl_icore_mmc_defconfig | 1 +\n configs/imx6qdl_icore_rqs_defconfig | 1 +\n include/configs/imx6-engicam.h | 22 +++----\n 9 files changed, 31 insertions(+), 187 deletions(-)","diff":"diff --git a/arch/arm/dts/imx6qdl-icore-rqs.dtsi b/arch/arm/dts/imx6qdl-icore-rqs.dtsi\nindex 8b9d5b4..65cbf5a 100644\n--- a/arch/arm/dts/imx6qdl-icore-rqs.dtsi\n+++ b/arch/arm/dts/imx6qdl-icore-rqs.dtsi\n@@ -100,6 +100,7 @@\n };\n \n &usdhc3 {\n+\tu-boot,dm-spl;\n \tpinctrl-names = \"default\";\n \tpinctrl-0 = <&pinctrl_usdhc3>;\n \tcd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;\n@@ -165,6 +166,7 @@\n \t};\n \n \tpinctrl_usdhc3: usdhc3grp {\n+\t\tu-boot,dm-spl;\n \t\tfsl,pins = <\n \t\t\tMX6QDL_PAD_SD3_CMD__SD3_CMD 0x17070\n \t\t\tMX6QDL_PAD_SD3_CLK__SD3_CLK 0x10070\ndiff --git a/arch/arm/dts/imx6qdl-icore.dtsi b/arch/arm/dts/imx6qdl-icore.dtsi\nindex a485c3e..06d9bc3 100644\n--- a/arch/arm/dts/imx6qdl-icore.dtsi\n+++ b/arch/arm/dts/imx6qdl-icore.dtsi\n@@ -118,6 +118,7 @@\n };\n \n &usdhc1 {\n+\tu-boot,dm-spl;\n \tpinctrl-names = \"default\";\n \tpinctrl-0 = <&pinctrl_usdhc1>;\n \tcd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;\n@@ -208,6 +209,7 @@\n \t};\n \n \tpinctrl_usdhc1: usdhc1grp {\n+\t\tu-boot,dm-spl;\n \t\tfsl,pins = <\n \t\t\tMX6QDL_PAD_SD1_CMD__SD1_CMD 0x17070\n \t\t\tMX6QDL_PAD_SD1_CLK__SD1_CLK 0x10070\ndiff --git a/arch/arm/dts/imx6qdl.dtsi b/arch/arm/dts/imx6qdl.dtsi\nindex b13b0b2..e04b570 100644\n--- a/arch/arm/dts/imx6qdl.dtsi\n+++ b/arch/arm/dts/imx6qdl.dtsi\n@@ -77,6 +77,7 @@\n \t\tcompatible = \"simple-bus\";\n \t\tinterrupt-parent = <&gpc>;\n \t\tranges;\n+\t\tu-boot,dm-spl;\n \n \t\tdma_apbh: dma-apbh@00110000 {\n \t\t\tcompatible = \"fsl,imx6q-dma-apbh\", \"fsl,imx28-dma-apbh\";\n@@ -225,6 +226,7 @@\n \t\t\t#size-cells = <1>;\n \t\t\treg = <0x02000000 0x100000>;\n \t\t\tranges;\n+\t\t\tu-boot,dm-spl;\n \n \t\t\tspba-bus@02000000 {\n \t\t\t\tcompatible = \"fsl,spba-bus\", \"simple-bus\";\n@@ -516,6 +518,7 @@\n \t\t\t\t#gpio-cells = <2>;\n \t\t\t\tinterrupt-controller;\n \t\t\t\t#interrupt-cells = <2>;\n+\t\t\t\tu-boot,dm-spl;\n \t\t\t};\n \n \t\t\tgpio2: gpio@020a0000 {\n@@ -805,6 +808,7 @@\n \t\t\tiomuxc: iomuxc@020e0000 {\n \t\t\t\tcompatible = \"fsl,imx6dl-iomuxc\", \"fsl,imx6q-iomuxc\";\n \t\t\t\treg = <0x020e0000 0x4000>;\n+\t\t\t\tu-boot,dm-spl;\n \t\t\t};\n \n \t\t\tldb: ldb@020e0008 {\n@@ -889,6 +893,7 @@\n \t\t\t#size-cells = <1>;\n \t\t\treg = <0x02100000 0x100000>;\n \t\t\tranges;\n+\t\t\tu-boot,dm-spl;\n \n \t\t\tcrypto: caam@2100000 {\n \t\t\t\tcompatible = \"fsl,sec-v4.0\";\ndiff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig\nindex 540f2b2..9f2b30c 100644\n--- a/arch/arm/mach-imx/mx6/Kconfig\n+++ b/arch/arm/mach-imx/mx6/Kconfig\n@@ -198,6 +198,10 @@ config TARGET_MX6Q_ICORE\n \tselect DM_THERMAL\n \tselect SUPPORT_SPL\n \tselect SPL_LOAD_FIT\n+\tselect SPL_DM if SPL\n+\tselect SPL_OF_CONTROL if SPL\n+\tselect SPL_SEPARATE_BSS if SPL\n+\tselect SPL_PINCTRL if SPL\n \n config TARGET_MX6Q_ICORE_RQS\n \tbool \"Support Engicam i.Core RQS\"\n@@ -213,6 +217,10 @@ config TARGET_MX6Q_ICORE_RQS\n \tselect DM_THERMAL\n \tselect SUPPORT_SPL\n \tselect SPL_LOAD_FIT\n+\tselect SPL_DM if SPL\n+\tselect SPL_OF_CONTROL if SPL\n+\tselect SPL_SEPARATE_BSS if SPL\n+\tselect SPL_PINCTRL if SPL\n \n config TARGET_MX6SABREAUTO\n \tbool \"mx6sabreauto\"\ndiff --git a/board/engicam/icorem6/icorem6.c b/board/engicam/icorem6/icorem6.c\nindex e173124..a967ccd 100644\n--- a/board/engicam/icorem6/icorem6.c\n+++ b/board/engicam/icorem6/icorem6.c\n@@ -7,7 +7,6 @@\n */\n \n #include \n-#include \n \n #include \n #include \n@@ -191,77 +190,3 @@ void setup_display(void)\n \twritel(reg, &iomux->gpr[3]);\n }\n #endif /* CONFIG_VIDEO_IPUV3 */\n-\n-#ifdef CONFIG_SPL_BUILD\n-/* MMC board initialization is needed till adding DM support in SPL */\n-#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)\n-#include \n-#include \n-\n-#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \\\n-\tPAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \\\n-\tPAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)\n-\n-static iomux_v3_cfg_t const usdhc1_pads[] = {\n-\tIOMUX_PADS(PAD_SD1_CLK__SD1_CLK\t| MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD1_CMD__SD1_CMD\t| MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)),/* CD */\n-};\n-\n-#define USDHC1_CD_GPIO\tIMX_GPIO_NR(1, 1)\n-\n-struct fsl_esdhc_cfg usdhc_cfg[1] = {\n-\t{USDHC1_BASE_ADDR, 0, 4},\n-};\n-\n-int board_mmc_getcd(struct mmc *mmc)\n-{\n-\tstruct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;\n-\tint ret = 0;\n-\n-\tswitch (cfg->esdhc_base) {\n-\tcase USDHC1_BASE_ADDR:\n-\t\tret = !gpio_get_value(USDHC1_CD_GPIO);\n-\t\tbreak;\n-\t}\n-\n-\treturn ret;\n-}\n-\n-int board_mmc_init(bd_t *bis)\n-{\n-\tint i, ret;\n-\n-\t/*\n-\t* According to the board_mmc_init() the following map is done:\n-\t* (U-boot device node) (Physical Port)\n-\t* mmc0\t\t\t\tUSDHC1\n-\t*/\n-\tfor (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {\n-\t\tswitch (i) {\n-\t\tcase 0:\n-\t\t\tSETUP_IOMUX_PADS(usdhc1_pads);\n-\t\t\tgpio_direction_input(USDHC1_CD_GPIO);\n-\t\t\tusdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\tprintf(\"Warning - USDHC%d controller not supporting\\n\",\n-\t\t\t i + 1);\n-\t\t\treturn 0;\n-\t\t}\n-\n-\t\tret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);\n-\t\tif (ret) {\n-\t\t\tprintf(\"Warning: failed to initialize mmc dev %d\\n\", i);\n-\t\t\treturn ret;\n-\t\t}\n-\t}\n-\n-\treturn 0;\n-}\n-#endif\n-#endif /* CONFIG_SPL_BUILD */\ndiff --git a/board/engicam/icorem6_rqs/icorem6_rqs.c b/board/engicam/icorem6_rqs/icorem6_rqs.c\nindex 599cea3..c0a6d4f 100644\n--- a/board/engicam/icorem6_rqs/icorem6_rqs.c\n+++ b/board/engicam/icorem6_rqs/icorem6_rqs.c\n@@ -6,21 +6,7 @@\n * SPDX-License-Identifier:\tGPL-2.0+\n */\n \n-#include \n-#include \n-\n-#include \n-#include \n-#include \n-\n-#include \n-#include \n-#include \n-#include \n #include \n-#include \n-\n-#include \"../common/board.h\"\n \n DECLARE_GLOBAL_DATA_PTR;\n \n@@ -35,93 +21,6 @@ int board_mmc_get_env_dev(int devno)\n #ifdef CONFIG_SPL_BUILD\n #include \n \n-/* MMC board initialization is needed till adding DM support in SPL */\n-#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)\n-#include \n-#include \n-\n-#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \\\n-\tPAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \\\n-\tPAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)\n-\n-static iomux_v3_cfg_t const usdhc3_pads[] = {\n-\tIOMUX_PADS(PAD_SD3_CLK__SD3_CLK\t| MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD3_CMD__SD3_CMD\t| MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-};\n-\n-static iomux_v3_cfg_t const usdhc4_pads[] = {\n-\tIOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-};\n-\n-struct fsl_esdhc_cfg usdhc_cfg[2] = {\n-\t{USDHC3_BASE_ADDR, 1, 4},\n-\t{USDHC4_BASE_ADDR, 1, 8},\n-};\n-\n-int board_mmc_getcd(struct mmc *mmc)\n-{\n-\tstruct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;\n-\tint ret = 0;\n-\n-\tswitch (cfg->esdhc_base) {\n-\tcase USDHC3_BASE_ADDR:\n-\tcase USDHC4_BASE_ADDR:\n-\t\tret = 1;\n-\t\tbreak;\n-\t}\n-\n-\treturn ret;\n-}\n-\n-int board_mmc_init(bd_t *bis)\n-{\n-\tint i, ret;\n-\n-\t/*\n-\t* According to the board_mmc_init() the following map is done:\n-\t* (U-boot device node) (Physical Port)\n-\t* mmc0\t\t\tUSDHC3\n-\t* mmc1\t\t\tUSDHC4\n-\t*/\n-\tfor (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {\n-\t\tswitch (i) {\n-\t\tcase 0:\n-\t\t\tSETUP_IOMUX_PADS(usdhc3_pads);\n-\t\t\tusdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);\n-\t\t\tbreak;\n-\t\tcase 1:\n-\t\t\tSETUP_IOMUX_PADS(usdhc4_pads);\n-\t\t\tusdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\tprintf(\"Warning - USDHC%d controller not supporting\\n\",\n-\t\t\t i + 1);\n-\t\t\treturn 0;\n-\t\t}\n-\n-\t\tret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);\n-\t\tif (ret) {\n-\t\t\tprintf(\"Warning: failed to initialize mmc dev %d\\n\", i);\n-\t\t\treturn ret;\n-\t\t}\n-\t}\n-\n-\treturn 0;\n-}\n-\n #ifdef CONFIG_ENV_IS_IN_MMC\n void board_boot_order(u32 *spl_boot_list)\n {\n@@ -147,5 +46,4 @@ void board_boot_order(u32 *spl_boot_list)\n \tspl_boot_list[0] = boot_dev;\n }\n #endif\n-#endif\n #endif /* CONFIG_SPL_BUILD */\ndiff --git a/configs/imx6qdl_icore_mmc_defconfig b/configs/imx6qdl_icore_mmc_defconfig\nindex 1b001df..221866a 100644\n--- a/configs/imx6qdl_icore_mmc_defconfig\n+++ b/configs/imx6qdl_icore_mmc_defconfig\n@@ -49,3 +49,4 @@ CONFIG_DEBUG_UART_CLOCK=24000000\n CONFIG_MXC_UART=y\n CONFIG_IMX_THERMAL=y\n CONFIG_VIDEO_IPUV3=y\n+CONFIG_SYS_MALLOC_F_LEN=0x2000\ndiff --git a/configs/imx6qdl_icore_rqs_defconfig b/configs/imx6qdl_icore_rqs_defconfig\nindex a57a992..e6b4dff 100644\n--- a/configs/imx6qdl_icore_rqs_defconfig\n+++ b/configs/imx6qdl_icore_rqs_defconfig\n@@ -41,3 +41,4 @@ CONFIG_FEC_MXC=y\n CONFIG_PINCTRL=y\n CONFIG_PINCTRL_IMX6=y\n CONFIG_MXC_UART=y\n+CONFIG_SYS_MALLOC_F_LEN=0x2000\ndiff --git a/include/configs/imx6-engicam.h b/include/configs/imx6-engicam.h\nindex c34dc30..ddbd6dd 100644\n--- a/include/configs/imx6-engicam.h\n+++ b/include/configs/imx6-engicam.h\n@@ -219,16 +219,18 @@\n \n # include \"imx6_spl.h\"\n # ifdef CONFIG_SPL_BUILD\n-# if defined(CONFIG_TARGET_MX6Q_ICORE_RQS) || defined(CONFIG_TARGET_MX6UL_ISIOT)\n-# define CONFIG_SYS_FSL_USDHC_NUM\t2\n-# else\n-# define CONFIG_SYS_FSL_USDHC_NUM\t1\n-# endif\n-\n-# define CONFIG_SYS_FSL_ESDHC_ADDR\t0\n-# undef CONFIG_DM_GPIO\n-# undef CONFIG_DM_MMC\n-# endif\n+# if defined(CONFIG_IMX6UL)\n+# if defined(CONFIG_TARGET_MX6UL_ISIOT)\n+# define CONFIG_SYS_FSL_USDHC_NUM\t2\n+# else\n+# define CONFIG_SYS_FSL_USDHC_NUM\t1\n+# endif\n+\n+# define CONFIG_SYS_FSL_ESDHC_ADDR\t0\n+# undef CONFIG_DM_GPIO\n+# undef CONFIG_DM_MMC\n+# endif /* CONFIG_IMX6UL */\n+# endif /* CONFIG_SPL_BUILD */\n #endif\n \n #endif /* __IMX6_ENGICAM_CONFIG_H */\n","prefixes":["U-Boot","5/6"]}