{"id":815482,"url":"http://patchwork.ozlabs.org/api/patches/815482/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170919115814.14724-2-marcandre.lureau@redhat.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170919115814.14724-2-marcandre.lureau@redhat.com>","list_archive_url":null,"date":"2017-09-19T11:58:11","name":"[v2,1/4] fw_cfg: add DMA register","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"e4ac5a8e6e5b86f9d5f30dbc6dd638d8fc851ff3","submitter":{"id":66774,"url":"http://patchwork.ozlabs.org/api/people/66774/?format=json","name":"Marc-André Lureau","email":"marcandre.lureau@redhat.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170919115814.14724-2-marcandre.lureau@redhat.com/mbox/","series":[{"id":3856,"url":"http://patchwork.ozlabs.org/api/series/3856/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=3856","date":"2017-09-19T11:58:10","name":"fw_cfg: add DMA operations & etc/vmcoreinfo support","version":2,"mbox":"http://patchwork.ozlabs.org/series/3856/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/815482/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/815482/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ext-mx03.extmail.prod.ext.phx2.redhat.com;\n\tdmarc=none (p=none dis=none) header.from=redhat.com","ext-mx03.extmail.prod.ext.phx2.redhat.com;\n\tspf=fail smtp.mailfrom=marcandre.lureau@redhat.com"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xxLxy3z71z9s7m\n\tfor ;\n\tTue, 19 Sep 2017 21:59:02 +1000 (AEST)","from localhost ([::1]:41995 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1duHB6-0007O6-KS\n\tfor incoming@patchwork.ozlabs.org; Tue, 19 Sep 2017 07:59:00 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:40556)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1duHAY-0007J0-DV\n\tfor qemu-devel@nongnu.org; Tue, 19 Sep 2017 07:58:27 -0400","from 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19 Sep 2017 13:58:11 +0200","Message-Id":"<20170919115814.14724-2-marcandre.lureau@redhat.com>","In-Reply-To":"<20170919115814.14724-1-marcandre.lureau@redhat.com>","References":"<20170919115814.14724-1-marcandre.lureau@redhat.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","X-Scanned-By":"MIMEDefang 2.79 on 10.5.11.11","X-Greylist":"Sender IP whitelisted, not delayed by milter-greylist-4.5.16\n\t(mx1.redhat.com [10.5.110.27]);\n\tTue, 19 Sep 2017 11:58:23 +0000 (UTC)","Content-Transfer-Encoding":"quoted-printable","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]","X-Received-From":"209.132.183.28","Subject":"[Qemu-devel] [PATCH v2 1/4] fw_cfg: add DMA register","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"=?utf-8?q?Marc-Andr=C3=A9_Lureau?= ,\n\tsomlo@cmu.edu, qemu-devel@nongnu.org, mst@redhat.com","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"From: Marc-André Lureau \n\nAdd an optional kernel module (or command line) parameter\nusing the following syntax:\n\n [fw_cfg.]ioport=@[::[:]]\n or\n [fw_cfg.]mmio=@[::[:]]\n\nand initializes the register address using given or default offset.\n\nSigned-off-by: Marc-André Lureau \n---\n drivers/firmware/qemu_fw_cfg.c | 53 ++++++++++++++++++++++++++++++++----------\n 1 file changed, 41 insertions(+), 12 deletions(-)","diff":"diff --git a/drivers/firmware/qemu_fw_cfg.c b/drivers/firmware/qemu_fw_cfg.c\nindex 0e2011636fbb..614037703530 100644\n--- a/drivers/firmware/qemu_fw_cfg.c\n+++ b/drivers/firmware/qemu_fw_cfg.c\n@@ -10,20 +10,21 @@\n * and select subsets of aarch64), a Device Tree node (on arm), or using\n * a kernel module (or command line) parameter with the following syntax:\n *\n- * [fw_cfg.]ioport=@[::]\n+ * [fw_cfg.]ioport=@[::[:]]\n * or\n- * [fw_cfg.]mmio=@[::]\n+ * [fw_cfg.]mmio=@[::[:]]\n *\n * where:\n * := size of ioport or mmio range\n * := physical base address of ioport or mmio range\n * := (optional) offset of control register\n * := (optional) offset of data register\n+ * := (optional) offset of dma register\n *\n * e.g.:\n- * fw_cfg.ioport=2@0x510:0:1\t\t(the default on x86)\n+ * fw_cfg.ioport=2@0x510:0:1:4\t\t(the default on x86)\n * or\n- * fw_cfg.mmio=0xA@0x9020000:8:0\t\t(the default on arm)\n+ * fw_cfg.mmio=0xA@0x9020000:8:0:16\t(the default on arm)\n */\n \n #include \n@@ -63,6 +64,7 @@ static resource_size_t fw_cfg_p_size;\n static void __iomem *fw_cfg_dev_base;\n static void __iomem *fw_cfg_reg_ctrl;\n static void __iomem *fw_cfg_reg_data;\n+static void __iomem *fw_cfg_reg_dma;\n \n /* atomic access to fw_cfg device (potentially slow i/o, so using mutex) */\n static DEFINE_MUTEX(fw_cfg_dev_lock);\n@@ -118,12 +120,14 @@ static void fw_cfg_io_cleanup(void)\n # if (defined(CONFIG_ARM) || defined(CONFIG_ARM64))\n # define FW_CFG_CTRL_OFF 0x08\n # define FW_CFG_DATA_OFF 0x00\n+# define FW_CFG_DMA_OFF 0x10\n # elif (defined(CONFIG_PPC_PMAC) || defined(CONFIG_SPARC32)) /* ppc/mac,sun4m */\n # define FW_CFG_CTRL_OFF 0x00\n # define FW_CFG_DATA_OFF 0x02\n # elif (defined(CONFIG_X86) || defined(CONFIG_SPARC64)) /* x86, sun4u */\n # define FW_CFG_CTRL_OFF 0x00\n # define FW_CFG_DATA_OFF 0x01\n+# define FW_CFG_DMA_OFF 0x04\n # else\n # error \"QEMU FW_CFG not available on this architecture!\"\n # endif\n@@ -133,7 +137,7 @@ static void fw_cfg_io_cleanup(void)\n static int fw_cfg_do_platform_probe(struct platform_device *pdev)\n {\n \tchar sig[FW_CFG_SIG_SIZE];\n-\tstruct resource *range, *ctrl, *data;\n+\tstruct resource *range, *ctrl, *data, *dma;\n \n \t/* acquire i/o range details */\n \tfw_cfg_is_mmio = false;\n@@ -170,6 +174,7 @@ static int fw_cfg_do_platform_probe(struct platform_device *pdev)\n \t/* were custom register offsets provided (e.g. on the command line)? */\n \tctrl = platform_get_resource_byname(pdev, IORESOURCE_REG, \"ctrl\");\n \tdata = platform_get_resource_byname(pdev, IORESOURCE_REG, \"data\");\n+\tdma = platform_get_resource_byname(pdev, IORESOURCE_REG, \"dma\");\n \tif (ctrl && data) {\n \t\tfw_cfg_reg_ctrl = fw_cfg_dev_base + ctrl->start;\n \t\tfw_cfg_reg_data = fw_cfg_dev_base + data->start;\n@@ -179,6 +184,13 @@ static int fw_cfg_do_platform_probe(struct platform_device *pdev)\n \t\tfw_cfg_reg_data = fw_cfg_dev_base + FW_CFG_DATA_OFF;\n \t}\n \n+\tif (dma)\n+\t\tfw_cfg_reg_dma = fw_cfg_dev_base + dma->start;\n+#ifdef FW_CFG_DMA_OFF\n+\telse\n+\t\tfw_cfg_reg_dma = fw_cfg_dev_base + FW_CFG_DMA_OFF;\n+#endif\n+\n \t/* verify fw_cfg device signature */\n \tfw_cfg_read_blob(FW_CFG_SIGNATURE, sig, 0, FW_CFG_SIG_SIZE);\n \tif (memcmp(sig, \"QEMU\", FW_CFG_SIG_SIZE) != 0) {\n@@ -628,6 +640,7 @@ static struct platform_device *fw_cfg_cmdline_dev;\n /* use special scanf/printf modifier for phys_addr_t, resource_size_t */\n #define PH_ADDR_SCAN_FMT \"@%\" __PHYS_ADDR_PREFIX \"i%n\" \\\n \t\t\t \":%\" __PHYS_ADDR_PREFIX \"i\" \\\n+\t\t\t \":%\" __PHYS_ADDR_PREFIX \"i%n\" \\\n \t\t\t \":%\" __PHYS_ADDR_PREFIX \"i%n\"\n \n #define PH_ADDR_PR_1_FMT \"0x%\" __PHYS_ADDR_PREFIX \"x@\" \\\n@@ -637,12 +650,15 @@ static struct platform_device *fw_cfg_cmdline_dev;\n \t\t\t \":%\" __PHYS_ADDR_PREFIX \"u\" \\\n \t\t\t \":%\" __PHYS_ADDR_PREFIX \"u\"\n \n+#define PH_ADDR_PR_4_FMT PH_ADDR_PR_3_FMT \\\n+\t\t\t \":%\" __PHYS_ADDR_PREFIX \"u\"\n+\n static int fw_cfg_cmdline_set(const char *arg, const struct kernel_param *kp)\n {\n-\tstruct resource res[3] = {};\n+\tstruct resource res[4] = {};\n \tchar *str;\n \tphys_addr_t base;\n-\tresource_size_t size, ctrl_off, data_off;\n+\tresource_size_t size, ctrl_off, data_off, dma_off;\n \tint processed, consumed = 0;\n \n \t/* only one fw_cfg device can exist system-wide, so if one\n@@ -658,19 +674,20 @@ static int fw_cfg_cmdline_set(const char *arg, const struct kernel_param *kp)\n \t/* consume \"\" portion of command line argument */\n \tsize = memparse(arg, &str);\n \n-\t/* get \"@[::]\" chunks */\n+\t/* get \"@[::[:]]\" chunks */\n \tprocessed = sscanf(str, PH_ADDR_SCAN_FMT,\n \t\t\t &base, &consumed,\n-\t\t\t &ctrl_off, &data_off, &consumed);\n+\t\t\t &ctrl_off, &data_off, &consumed,\n+\t\t\t &dma_off, &consumed);\n \n-\t/* sscanf() must process precisely 1 or 3 chunks:\n+\t/* sscanf() must process precisely 1, 3 or 4 chunks:\n \t * is mandatory, optionally followed by \n-\t * and ;\n+\t * and , and ;\n \t * there must be no extra characters after the last chunk,\n \t * so str[consumed] must be '\\0'.\n \t */\n \tif (str[consumed] ||\n-\t (processed != 1 && processed != 3))\n+\t (processed != 1 && processed != 3 && process != 4))\n \t\treturn -EINVAL;\n \n \tres[0].start = base;\n@@ -687,6 +704,11 @@ static int fw_cfg_cmdline_set(const char *arg, const struct kernel_param *kp)\n \t\tres[2].start = data_off;\n \t\tres[2].flags = IORESOURCE_REG;\n \t}\n+\tif (processed > 3) {\n+\t\tres[3].name = \"dma\";\n+\t\tres[3].start = dma_off;\n+\t\tres[3].flags = IORESOURCE_REG;\n+\t}\n \n \t/* \"processed\" happens to nicely match the number of resources\n \t * we need to pass in to this platform device.\n@@ -721,6 +743,13 @@ static int fw_cfg_cmdline_get(char *buf, const struct kernel_param *kp)\n \t\t\t\tfw_cfg_cmdline_dev->resource[0].start,\n \t\t\t\tfw_cfg_cmdline_dev->resource[1].start,\n \t\t\t\tfw_cfg_cmdline_dev->resource[2].start);\n+\tcase 4:\n+\t\treturn snprintf(buf, PAGE_SIZE, PH_ADDR_PR_4_FMT,\n+\t\t\t\tresource_size(&fw_cfg_cmdline_dev->resource[0]),\n+\t\t\t\tfw_cfg_cmdline_dev->resource[0].start,\n+\t\t\t\tfw_cfg_cmdline_dev->resource[1].start,\n+\t\t\t\tfw_cfg_cmdline_dev->resource[2].start,\n+\t\t\t\tfw_cfg_cmdline_dev->resource[3].start);\n \t}\n \n \t/* Should never get here */\n","prefixes":["v2","1/4"]}