{"id":815437,"url":"http://patchwork.ozlabs.org/api/patches/815437/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1505818630-49239-1-git-send-email-david.wu@rock-chips.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1505818630-49239-1-git-send-email-david.wu@rock-chips.com>","list_archive_url":null,"date":"2017-09-19T10:57:10","name":"[U-Boot,U-Boot,v2,05/14] clk: rockchip: Add rk3328 SARADC clock support","commit_ref":null,"pull_url":null,"state":"superseded","archived":false,"hash":"773c799005d805961efb27d6b1dbcda8fbb930bf","submitter":{"id":68083,"url":"http://patchwork.ozlabs.org/api/people/68083/?format=json","name":"David Wu","email":"david.wu@rock-chips.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1505818630-49239-1-git-send-email-david.wu@rock-chips.com/mbox/","series":[{"id":3839,"url":"http://patchwork.ozlabs.org/api/series/3839/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=3839","date":"2017-09-19T10:53:11","name":"Add rockchip SARADC support","version":2,"mbox":"http://patchwork.ozlabs.org/series/3839/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/815437/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/815437/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xxKbk2dlPz9sBZ\n\tfor ;\n\tTue, 19 Sep 2017 20:58:10 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 0A35EC21F29; Tue, 19 Sep 2017 10:57:59 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 19D9BC21F00;\n\tTue, 19 Sep 2017 10:57:56 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid B3A9AC21F00; Tue, 19 Sep 2017 10:57:54 +0000 (UTC)","from localhost by lists.denx.de with SpamAssassin (version 3.4.0); \n\tTue, 19 Sep 2017 10:57:54 +0000"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-1.0 required=5.0 tests=ALL_TRUSTED\n\tautolearn=unavailable autolearn_force=no version=3.4.0","From":"David Wu ","To":"sjg@chromium.org,\n\tphilipp.tomsich@theobroma-systems.com","Date":"Tue, 19 Sep 2017 18:57:10 +0800","Message-Id":"<1505818630-49239-1-git-send-email-david.wu@rock-chips.com>","MIME-Version":"1.0","Content-Type":"multipart/mixed; boundary=\"----------=_59C0F832.0A30BA4C\"","Cc":"huangtao@rock-chips.com, zhangqing@rock-chips.com, u-boot@lists.denx.de, \n\tDavid Wu , andy.yan@rock-chips.com,\n\tchenjh@rock-chips.com","Subject":"[U-Boot] [U-Boot, v2,\n\t05/14] clk: rockchip: Add rk3328 SARADC clock support","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"Spam detection software, running on the system \"lists.denx.de\",\nhas identified this incoming email as possible spam. The original\nmessage has been attached to this so you can view it or label\nsimilar future email. If you have any questions, see\n@@CONTACT_ADDRESS@@ for details.\n\nContent preview: The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).\n SARADC integer divider control register is 10-bits width. Signed-off-by:\n David Wu Acked-by: Philipp Tomsich \n Reviewed-by: Philipp Tomsich ---\n [...] \n\nContent analysis details: (6.9 points, 5.0 required)\n\n pts rule name description\n---- ---------------------- --------------------------------------------------\n 0.6 RCVD_IN_SORBS_WEB RBL: SORBS: sender is an abusable web server\n [58.22.7.114 listed in dnsbl.sorbs.net]\n 1.2 RCVD_IN_BL_SPAMCOP_NET RBL: Received via a relay in bl.spamcop.net\n [Blocked - see ]\n 2.7 RCVD_IN_PSBL RBL: Received via a relay in PSBL\n [211.157.147.135 listed in psbl.surriel.com]\n 2.4 RCVD_IN_MSPIKE_L5 RBL: Very bad reputation (-5)\n [211.157.147.135 listed in bl.mailspike.net]\n 0.0 RCVD_IN_MSPIKE_BL Mailspike blacklisted\nThe clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).\nSARADC integer divider control register is 10-bits width.\n\nSigned-off-by: David Wu \nAcked-by: Philipp Tomsich \nReviewed-by: Philipp Tomsich \n---\n\nChange in v2:\n - Use extract_bits.\n\n drivers/clk/rockchip/clk_rk3328.c | 35 ++++++++++++++++++++++++++++++++++-\n 1 file changed, 34 insertions(+), 1 deletion(-)","diff":"diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c\nindex c3a6650..540d910 100644\n--- a/drivers/clk/rockchip/clk_rk3328.c\n+++ b/drivers/clk/rockchip/clk_rk3328.c\n@@ -5,6 +5,7 @@\n */\n \n #include \n+#include \n #include \n #include \n #include \n@@ -114,7 +115,8 @@ enum {\n \n \t/* CLKSEL_CON23 */\n \tCLK_SARADC_DIV_CON_SHIFT\t= 0,\n-\tCLK_SARADC_DIV_CON_MASK\t\t= 0x3ff << CLK_SARADC_DIV_CON_SHIFT,\n+\tCLK_SARADC_DIV_CON_MASK\t\t= GENMASK(9, 0),\n+\tCLK_SARADC_DIV_CON_WIDTH\t= 10,\n \n \t/* CLKSEL_CON24 */\n \tCLK_PWM_PLL_SEL_CPLL\t\t= 0,\n@@ -478,6 +480,31 @@ static ulong rk3328_pwm_set_clk(struct rk3328_cru *cru, uint hz)\n \treturn DIV_TO_RATE(GPLL_HZ, div);\n }\n \n+static ulong rk3328_saradc_get_clk(struct rk3328_cru *cru)\n+{\n+\tu32 div, val;\n+\n+\tval = readl(&cru->clksel_con[23]);\n+\tdiv = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,\n+\t\t\t CLK_SARADC_DIV_CON_WIDTH);\n+\n+\treturn DIV_TO_RATE(OSC_HZ, div);\n+}\n+\n+static ulong rk3328_saradc_set_clk(struct rk3328_cru *cru, uint hz)\n+{\n+\tint src_clk_div;\n+\n+\tsrc_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;\n+\tassert(src_clk_div < 128);\n+\n+\trk_clrsetreg(&cru->clksel_con[23],\n+\t\t CLK_SARADC_DIV_CON_MASK,\n+\t\t src_clk_div << CLK_SARADC_DIV_CON_SHIFT);\n+\n+\treturn rk3328_saradc_get_clk(cru);\n+}\n+\n static ulong rk3328_clk_get_rate(struct clk *clk)\n {\n \tstruct rk3328_clk_priv *priv = dev_get_priv(clk->dev);\n@@ -501,6 +528,9 @@ static ulong rk3328_clk_get_rate(struct clk *clk)\n \tcase SCLK_PWM:\n \t\trate = rk3328_pwm_get_clk(priv->cru);\n \t\tbreak;\n+\tcase SCLK_SARADC:\n+\t\trate = rk3328_saradc_get_clk(priv->cru);\n+\t\tbreak;\n \tdefault:\n \t\treturn -ENOENT;\n \t}\n@@ -531,6 +561,9 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate)\n \tcase SCLK_PWM:\n \t\tret = rk3328_pwm_set_clk(priv->cru, rate);\n \t\tbreak;\n+\tcase SCLK_SARADC:\n+\t\tret = rk3328_saradc_set_clk(priv->cru, rate);\n+\t\tbreak;\n \tdefault:\n \t\treturn -ENOENT;\n \t}\n","prefixes":["U-Boot","U-Boot","v2","05/14"]}