{"id":815385,"url":"http://patchwork.ozlabs.org/api/patches/815385/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20170919092658.22482-5-Zhiqiang.Hou@nxp.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170919092658.22482-5-Zhiqiang.Hou@nxp.com>","list_archive_url":null,"date":"2017-09-19T09:26:57","name":"[4/5] arm64: dts: ls1012a: Add PCIe controller DT node","commit_ref":null,"pull_url":null,"state":"accepted","archived":false,"hash":"d1b3766340be585f718c7e862edeb9cebb01d2e9","submitter":{"id":67929,"url":"http://patchwork.ozlabs.org/api/people/67929/?format=json","name":"Z.Q. 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Tue, 19 Sep 2017 09:44:41 +0000","from tx30smr01.am.freescale.net (192.88.168.50) by\n\tBL2FFO11OLC005.mail.protection.outlook.com (10.173.160.91) with\n\tMicrosoft\n\tSMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id\n\t15.20.35.14 via Frontend Transport; Tue, 19 Sep 2017 09:44:41 +0000","from titan.ap.freescale.net ([10.192.208.233])\n\tby tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id\n\tv8J9iINR014190; Tue, 19 Sep 2017 02:44:37 -0700"],"Received-SPF":"Fail (protection.outlook.com: domain of nxp.com does not\n\tdesignate 192.88.168.50 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=192.88.168.50; helo=tx30smr01.am.freescale.net;","From":"Zhiqiang Hou ","To":", ,\n\t, ,\n\t, ,\n\t, ,\n\t, , ,\n\t, ","CC":"Hou Zhiqiang ","Subject":"[PATCH 4/5] arm64: dts: ls1012a: Add PCIe controller DT node","Date":"Tue, 19 Sep 2017 17:26:57 +0800","Message-ID":"<20170919092658.22482-5-Zhiqiang.Hou@nxp.com>","X-Mailer":"git-send-email 2.14.1","In-Reply-To":"<20170919092658.22482-1-Zhiqiang.Hou@nxp.com>","References":"<20170919092658.22482-1-Zhiqiang.Hou@nxp.com>","X-EOPAttributedMessage":"0","X-Matching-Connectors":"131502878820528731;\n\t(91ab9b29-cfa4-454e-5278-08d120cd25b8); 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","X-Forefront-PRVS":"04359FAD81","SpamDiagnosticOutput":"1:99","SpamDiagnosticMetadata":"NSPM","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"19 Sep 2017 09:44:41.8812\n\t(UTC)","X-MS-Exchange-CrossTenant-Id":"5afe0b00-7697-4969-b663-5eab37d5f47e","X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp":"TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e;\n\tIp=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net]","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"CO2PR03MB2360","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"},"content":"From: Hou Zhiqiang \n\nAdd PCIe controller node for ls1012a platform.\n\nSigned-off-by: Hou Zhiqiang \n---\n arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 24 ++++++++++++++++++++++++\n 1 file changed, 24 insertions(+)","diff":"diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi\nindex a7698ac7264b..140570d45ff3 100644\n--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi\n+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi\n@@ -478,5 +478,29 @@\n \t\t\tmsi-controller;\n \t\t\tinterrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;\n \t\t};\n+\n+\t\tpcie@3400000 {\n+\t\t\tcompatible = \"fsl,ls1012a-pcie\", \"snps,dw-pcie\";\n+\t\t\treg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */\n+\t\t\t 0x40 0x00000000 0x0 0x00002000>; /* configuration space */\n+\t\t\treg-names = \"regs\", \"config\";\n+\t\t\tinterrupts = <0 118 0x4>, /* controller interrupt */\n+\t\t\t\t <0 117 0x4>; /* PME interrupt */\n+\t\t\tinterrupt-names = \"aer\", \"pme\";\n+\t\t\t#address-cells = <3>;\n+\t\t\t#size-cells = <2>;\n+\t\t\tdevice_type = \"pci\";\n+\t\t\tnum-lanes = <4>;\n+\t\t\tbus-range = <0x0 0xff>;\n+\t\t\tranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */\n+\t\t\t\t 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */\n+\t\t\tmsi-parent = <&msi>;\n+\t\t\t#interrupt-cells = <1>;\n+\t\t\tinterrupt-map-mask = <0 0 0 7>;\n+\t\t\tinterrupt-map = <0000 0 0 1 &gic 0 110 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t\t<0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t\t<0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t\t<0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t};\n \t};\n };\n","prefixes":["4/5"]}