{"id":815371,"url":"http://patchwork.ozlabs.org/api/patches/815371/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1505812951-25088-13-git-send-email-chin.liang.see@intel.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1505812951-25088-13-git-send-email-chin.liang.see@intel.com>","list_archive_url":null,"date":"2017-09-19T09:22:29","name":"[U-Boot,12/14] ddr: altera: stratix10: Add DDR support for Stratix10 SoC","commit_ref":null,"pull_url":null,"state":"superseded","archived":false,"hash":"194a3ce207f6dea4883f87031e6c6bae14ea9d2c","submitter":{"id":70182,"url":"http://patchwork.ozlabs.org/api/people/70182/?format=json","name":"See, Chin Liang","email":"chin.liang.see@intel.com"},"delegate":{"id":1699,"url":"http://patchwork.ozlabs.org/api/users/1699/?format=json","username":"marex","first_name":"Marek","last_name":"Vasut","email":"marek.vasut@gmail.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1505812951-25088-13-git-send-email-chin.liang.see@intel.com/mbox/","series":[{"id":3810,"url":"http://patchwork.ozlabs.org/api/series/3810/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=3810","date":"2017-09-19T09:22:17","name":"Enable Stratix10 SoC support","version":1,"mbox":"http://patchwork.ozlabs.org/series/3810/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/815371/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/815371/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xxHjQ6X6xz9sMN\n\tfor ;\n\tTue, 19 Sep 2017 19:32:58 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 9B8ABC21F0E; Tue, 19 Sep 2017 09:27:16 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id DEA2BC21EEC;\n\tTue, 19 Sep 2017 09:24:24 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 73928C21EDC; Tue, 19 Sep 2017 09:23:41 +0000 (UTC)","from mga14.intel.com (mga14.intel.com [192.55.52.115])\n\tby lists.denx.de (Postfix) with ESMTPS id 4ADB9C21EF0\n\tfor ; Tue, 19 Sep 2017 09:23:35 +0000 (UTC)","from fmsmga002.fm.intel.com ([10.253.24.26])\n\tby fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t19 Sep 2017 02:23:34 -0700","from pg-interactive1.altera.com ([137.57.137.156])\n\tby fmsmga002.fm.intel.com with ESMTP; 19 Sep 2017 02:23:02 -0700"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-5.0 required=5.0 tests=RCVD_IN_DNSWL_HI\n\tautolearn=unavailable autolearn_force=no version=3.4.0","X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos; i=\"5.42,417,1500966000\"; d=\"scan'208\";\n\ta=\"1220782436\"","From":"chin.liang.see@intel.com","To":"u-boot@lists.denx.de,\n\tMarek Vasut ","Date":"Tue, 19 Sep 2017 17:22:29 +0800","Message-Id":"<1505812951-25088-13-git-send-email-chin.liang.see@intel.com>","X-Mailer":"git-send-email 2.2.2","In-Reply-To":"<1505812951-25088-1-git-send-email-chin.liang.see@intel.com>","References":"<1505812951-25088-1-git-send-email-chin.liang.see@intel.com>","Cc":"Tien Fong Chee ,\n\tChin Liang See ","Subject":"[U-Boot] [PATCH 12/14] ddr: altera: stratix10: Add DDR support for\n\tStratix10 SoC","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"From: Chin Liang See \n\nAdd DDR support for Stratix SoC\n\nSigned-off-by: Chin Liang See \n---\n arch/arm/mach-socfpga/include/mach/sdram_s10.h | 333 +++++++++++++++++++++\n drivers/ddr/altera/Makefile | 1 +\n drivers/ddr/altera/sdram_s10.c | 382 +++++++++++++++++++++++++\n 3 files changed, 716 insertions(+)\n create mode 100644 arch/arm/mach-socfpga/include/mach/sdram_s10.h\n create mode 100644 drivers/ddr/altera/sdram_s10.c","diff":"diff --git a/arch/arm/mach-socfpga/include/mach/sdram_s10.h b/arch/arm/mach-socfpga/include/mach/sdram_s10.h\nnew file mode 100644\nindex 0000000..d0fd958\n--- /dev/null\n+++ b/arch/arm/mach-socfpga/include/mach/sdram_s10.h\n@@ -0,0 +1,333 @@\n+/*\n+ * Copyright (C) 2016-2017 Intel Corporation \n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0\n+ */\n+\n+#ifndef\t_SDRAM_S10_H_\n+#define\t_SDRAM_S10_H_\n+\n+unsigned long sdram_calculate_size(void);\n+int sdram_mmr_init_full(unsigned int sdr_phy_reg);\n+int sdram_calibration_full(void);\n+\n+#define DDR_TWR\t\t\t\t15\n+#define DDR_READ_LATENCY_DELAY\t\t40\n+#define DDR_ACTIVATE_FAWBANK\t\t0x1\n+\n+\n+struct socfpga_ecc_hmc {\n+\tuint32_t ip_rev_id;\n+\tuint32_t _pad_0x4_0x7;\n+\tuint32_t ddrioctrl;\n+\tuint32_t ddrcalstat;\n+\tuint32_t mpr_0beat1;\n+\tuint32_t mpr_1beat1;\n+\tuint32_t mpr_2beat1;\n+\tuint32_t mpr_3beat1;\n+\tuint32_t mpr_4beat1;\n+\tuint32_t mpr_5beat1;\n+\tuint32_t mpr_6beat1;\n+\tuint32_t mpr_7beat1;\n+\tuint32_t mpr_8beat1;\n+\tuint32_t mpr_0beat2;\n+\tuint32_t mpr_1beat2;\n+\tuint32_t mpr_2beat2;\n+\tuint32_t mpr_3beat2;\n+\tuint32_t mpr_4beat2;\n+\tuint32_t mpr_5beat2;\n+\tuint32_t mpr_6beat2;\n+\tuint32_t mpr_7beat2;\n+\tuint32_t mpr_8beat2;\n+\tuint32_t _pad_0x58_0x5f[2];\n+\tuint32_t auto_precharge;\n+\tuint32_t _pad_0x64_0xdf[31];\n+\tuint32_t dramaddrwidth;\n+\tuint32_t _pad_0xe4_0xff[7];\n+\tuint32_t eccctrl;\n+\tuint32_t eccctrl2;\n+\tuint32_t _pad_0x108_0x10f[2];\n+\tuint32_t errinten;\n+\tuint32_t errintens;\n+\tuint32_t errintenr;\n+\tuint32_t intmode;\n+\tuint32_t intstat;\n+\tuint32_t diaginttest;\n+\tuint32_t modstat;\n+\tuint32_t derraddra;\n+\tuint32_t serraddra;\n+\tuint32_t _pad_0x134_0x137;\n+\tuint32_t autowb_corraddr;\n+\tuint32_t serrcntreg;\n+\tuint32_t autowb_drop_cntreg;\n+\tuint32_t ecc_reg2wreccdatabus;\n+\tuint32_t ecc_rdeccdata2regbus;\n+\tuint32_t ecc_reg2rdeccdatabus;\n+\tuint32_t ecc_diagon;\n+\tuint32_t ecc_decstat;\n+\tuint32_t _pad_0x158_0x15f[2];\n+\tuint32_t ecc_errgenaddr_0;\n+\tuint32_t ecc_errgenaddr_1;\n+\tuint32_t ecc_errgenaddr_2;\n+\tuint32_t ecc_errgenaddr_3;\n+\tuint32_t ecc_ref2rddatabus_beat0;\n+\tuint32_t ecc_ref2rddatabus_beat1;\n+\tuint32_t ecc_ref2rddatabus_beat2;\n+\tuint32_t ecc_ref2rddatabus_beat3;\n+\tuint32_t ecc_errgenhaddr_0;\n+\tuint32_t ecc_errgenhaddr_1;\n+\tuint32_t ecc_errgenhaddr_2;\n+\tuint32_t ecc_errgenhaddr_3;\n+\tuint32_t ecc_rdeccdata2regbus_beat0;\n+\tuint32_t ecc_rdeccdata2regbus_beat1;\n+\tuint32_t ecc_rdeccdata2regbus_beat2;\n+\tuint32_t ecc_rdeccdata2regbus_beat3;\n+\tuint32_t _pad_0x1a0_0x1af[4];\n+\tuint32_t derrhaddr;\n+\tuint32_t serrhaddr;\n+\tuint32_t _pad_0x1b8_0x1bb;\n+\tuint32_t autowb_corrhaddr;\n+\tuint32_t _pad_0x1c0_0x20f[20];\n+\tuint32_t hpsintfcsel;\n+\tuint32_t rsthandshakectrl;\n+\tuint32_t rsthandshakestat;\n+};\n+\n+struct socfpga_noc_ddr_scheduler {\n+\tuint32_t main_scheduler_id_coreid;\n+\tuint32_t main_scheduler_id_revisionid;\n+\tuint32_t main_scheduler_ddrconf;\n+\tuint32_t main_scheduler_ddrtiming;\n+\tuint32_t main_scheduler_ddrmode;\n+\tuint32_t main_scheduler_readlatency;\n+\tuint32_t _pad_0x18_0x37[8];\n+\tuint32_t main_scheduler_activate;\n+\tuint32_t main_scheduler_devtodev;\n+\tuint32_t main_scheduler_ddr4timing;\n+};\n+\n+struct socfpga_io48_mmr {\n+\tuint32_t dbgcfg0;\n+\tuint32_t dbgcfg1;\n+\tuint32_t dbgcfg2;\n+\tuint32_t dbgcfg3;\n+\tuint32_t dbgcfg4;\n+\tuint32_t dbgcfg5;\n+\tuint32_t dbgcfg6;\n+\tuint32_t reserve0;\n+\tuint32_t reserve1;\n+\tuint32_t reserve2;\n+\tuint32_t ctrlcfg0;\n+\tuint32_t ctrlcfg1;\n+\tuint32_t ctrlcfg2;\n+\tuint32_t ctrlcfg3;\n+\tuint32_t ctrlcfg4;\n+\tuint32_t ctrlcfg5;\n+\tuint32_t ctrlcfg6;\n+\tuint32_t ctrlcfg7;\n+\tuint32_t ctrlcfg8;\n+\tuint32_t ctrlcfg9;\n+\tuint32_t dramtiming0;\n+\tuint32_t dramodt0;\n+\tuint32_t dramodt1;\n+\tuint32_t sbcfg0;\n+\tuint32_t sbcfg1;\n+\tuint32_t sbcfg2;\n+\tuint32_t sbcfg3;\n+\tuint32_t sbcfg4;\n+\tuint32_t sbcfg5;\n+\tuint32_t sbcfg6;\n+\tuint32_t sbcfg7;\n+\tuint32_t caltiming0;\n+\tuint32_t caltiming1;\n+\tuint32_t caltiming2;\n+\tuint32_t caltiming3;\n+\tuint32_t caltiming4;\n+\tuint32_t caltiming5;\n+\tuint32_t caltiming6;\n+\tuint32_t caltiming7;\n+\tuint32_t caltiming8;\n+\tuint32_t caltiming9;\n+\tuint32_t caltiming10;\n+\tuint32_t dramaddrw;\n+\tuint32_t sideband0;\n+\tuint32_t sideband1;\n+\tuint32_t sideband2;\n+\tuint32_t sideband3;\n+\tuint32_t sideband4;\n+\tuint32_t sideband5;\n+\tuint32_t sideband6;\n+\tuint32_t sideband7;\n+\tuint32_t sideband8;\n+\tuint32_t sideband9;\n+\tuint32_t sideband10;\n+\tuint32_t sideband11;\n+\tuint32_t sideband12;\n+\tuint32_t sideband13;\n+\tuint32_t sideband14;\n+\tuint32_t sideband15;\n+\tuint32_t dramsts;\n+\tuint32_t dbgdone;\n+\tuint32_t dbgsignals;\n+\tuint32_t dbgreset;\n+\tuint32_t dbgmatch;\n+\tuint32_t counter0mask;\n+\tuint32_t counter1mask;\n+\tuint32_t counter0match;\n+\tuint32_t counter1match;\n+\tuint32_t niosreserve0;\n+\tuint32_t niosreserve1;\n+\tuint32_t niosreserve2;\n+};\n+\n+union dramaddrw_reg {\n+\tstruct {\n+\t\tu32 cfg_col_addr_width:5;\n+\t\tu32 cfg_row_addr_width:5;\n+\t\tu32 cfg_bank_addr_width:4;\n+\t\tu32 cfg_bank_group_addr_width:2;\n+\t\tu32 cfg_cs_addr_width:3;\n+\t\tu32 reserved:13;\n+\t};\n+\tu32 word;\n+};\n+\n+union ctrlcfg0_reg {\n+\tstruct {\n+\t\tu32 cfg_mem_type:4;\n+\t\tu32 cfg_dimm_type:3;\n+\t\tu32 cfg_ac_pos:2;\n+\t\tu32 cfg_ctrl_burst_len:5;\n+\t\tu32 reserved:18; /* Other fields unused */\n+\t};\n+\tu32 word;\n+};\n+\n+union ctrlcfg1_reg {\n+\tstruct {\n+\t\tu32 cfg_dbc3_burst_len:5;\n+\t\tu32 cfg_addr_order:2;\n+\t\tu32 cfg_ctrl_enable_ecc:1;\n+\t\tu32 reserved:24; /* Other fields unused */\n+\t};\n+\tu32 word;\n+};\n+\n+union dramtiming0_reg {\n+\tstruct {\n+\t\tu32 cfg_tcl:6;\n+\t\tu32 reserved:8; /* Other fields unused */\n+\t};\n+\tu32 word;\n+};\n+\n+union caltiming0_reg {\n+\tstruct {\n+\t\tu32 cfg_act_to_rdwr:6;\n+\t\tu32 cfg_act_to_pch:6;\n+\t\tu32 cfg_act_to_act:6;\n+\t\tu32 cfg_act_to_act_db:6;\n+\t\tu32 reserved:8; /* Other fields unused */\n+\t};\n+\tu32 word;\n+};\n+\n+union caltiming1_reg {\n+\tstruct {\n+\t\tu32 cfg_rd_to_rd:6;\n+\t\tu32 cfg_rd_to_rd_dc:6;\n+\t\tu32 cfg_rd_to_rd_db:6;\n+\t\tu32 cfg_rd_to_wr:6;\n+\t\tu32 cfg_rd_to_wr_dc:6;\n+\t\tu32 reserved:2;\n+\t};\n+\tu32 word;\n+};\n+\n+union caltiming2_reg {\n+\tstruct {\n+\t\tu32 cfg_rd_to_wr_db:6;\n+\t\tu32 cfg_rd_to_pch:6;\n+\t\tu32 cfg_rd_ap_to_valid:6;\n+\t\tu32 cfg_wr_to_wr:6;\n+\t\tu32 cfg_wr_to_wr_dc:6;\n+\t\tu32 reserved:2;\n+\t};\n+\tu32 word;\n+};\n+\n+union caltiming3_reg {\n+\tstruct {\n+\t\tu32 cfg_wr_to_wr_db:6;\n+\t\tu32 cfg_wr_to_rd:6;\n+\t\tu32 cfg_wr_to_rd_dc:6;\n+\t\tu32 cfg_wr_to_rd_db:6;\n+\t\tu32 cfg_wr_to_pch:6;\n+\t\tu32 reserved:2;\n+\t};\n+\tu32 word;\n+};\n+\n+union caltiming4_reg {\n+\tstruct {\n+\t\tu32 cfg_wr_ap_to_valid:6;\n+\t\tu32 cfg_pch_to_valid:6;\n+\t\tu32 cfg_pch_all_to_valid:6;\n+\t\tu32 cfg_arf_to_valid:8;\n+\t\tu32 cfg_pdn_to_valid:6;\n+\t};\n+\tu32 word;\n+};\n+\n+union caltiming9_reg {\n+\tstruct {\n+\t\tu32 cfg_4_act_to_act:8;\n+\t\tu32 reserved:24;\n+\t};\n+\tu32 word;\n+};\n+\n+#define DDR_SCHED_DDRTIMING_ACTTOACT_OFFSET\t0\n+#define DDR_SCHED_DDRTIMING_RDTOMISS_OFFSET\t6\n+#define DDR_SCHED_DDRTIMING_WRTOMISS_OFFSET\t12\n+#define DDR_SCHED_DDRTIMING_BURSTLEN_OFFSET\t18\n+#define DDR_SCHED_DDRTIMING_RDTOWR_OFFSET\t21\n+#define DDR_SCHED_DDRTIMING_WRTORD_OFFSET\t26\n+#define DDR_SCHED_DDRTIMING_BWRATIO_OFFSET\t31\n+#define DDR_SCHED_DDRMOD_BWRATIOEXTENDED_OFFSET\t1\n+#define DDR_SCHED_ACTIVATE_RRD_OFFSET\t\t0\n+#define DDR_SCHED_ACTIVATE_FAW_OFFSET\t\t4\n+#define DDR_SCHED_ACTIVATE_FAWBANK_OFFSET\t10\n+#define DDR_SCHED_DEVTODEV_BUSRDTORD_OFFSET\t0\n+#define DDR_SCHED_DEVTODEV_BUSRDTOWR_OFFSET\t2\n+#define DDR_SCHED_DEVTODEV_BUSWRTORD_OFFSET\t4\n+#define DDR_HMC_DDRIOCTRL_IOSIZE_MSK\t\t0x00000003\n+#define DDR_HMC_DDRCALSTAT_CAL_MSK\t\t0x00000001\n+#define DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK\t0x00010000\n+#define DDR_HMC_ECCCTL_CNT_RST_SET_MSK\t\t0x00000100\n+#define DDR_HMC_ECCCTL_ECC_EN_SET_MSK\t\t0x00000001\n+#define DDR_HMC_ECCCTL2_RMW_EN_SET_MSK\t\t0x00000100\n+#define DDR_HMC_ECCCTL2_AWB_EN_SET_MSK\t\t0x00000001\n+#define DDR_HMC_RSTHANDSHAKE_MASK\t\t0x000000ff\n+#define DDR_HMC_CORE2SEQ_INT_REQ\t\t0xF\n+#define DDR_HMC_SEQ2CORE_INT_RESP_MASK\t\t0x8\n+#define DDR_HMC_HPSINTFCSEL_ENABLE_MASK\t\t0x001f1f1f\n+\n+#define CCU_CPU0_MPRT_ADBASE_DDRREG_ADDR\t0xf7004400\n+#define CCU_CPU0_MPRT_ADBASE_MEMSPACE0_ADDR\t0xf70045c0\n+#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1A_ADDR\t0xf70045e0\n+#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1B_ADDR\t0xf7004600\n+#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1C_ADDR\t0xf7004620\n+#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1D_ADDR\t0xf7004640\n+#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1E_ADDR\t0xf7004660\n+\n+#define CCU_IOM_MPRT_ADBASE_MEMSPACE0_ADDR\t0xf7018560\n+#define CCU_IOM_MPRT_ADBASE_MEMSPACE1A_ADDR\t0xf7018580\n+#define CCU_IOM_MPRT_ADBASE_MEMSPACE1B_ADDR\t0xf70185a0\n+#define CCU_IOM_MPRT_ADBASE_MEMSPACE1C_ADDR\t0xf70185c0\n+#define CCU_IOM_MPRT_ADBASE_MEMSPACE1D_ADDR\t0xf70185e0\n+#define CCU_IOM_MPRT_ADBASE_MEMSPACE1E_ADDR\t0xf7018600\n+\n+#define CCU_ADBASE_DI_MASK\t\t\t0x00000010\n+\n+#endif /* _SDRAM_S10_H_ */\ndiff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile\nindex bdd2872..943b6cd 100644\n--- a/drivers/ddr/altera/Makefile\n+++ b/drivers/ddr/altera/Makefile\n@@ -10,4 +10,5 @@\n \n ifdef CONFIG_ALTERA_SDRAM\n obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram.o sequencer.o\n+obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_s10.o\n endif\ndiff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c\nnew file mode 100644\nindex 0000000..c488caf\n--- /dev/null\n+++ b/drivers/ddr/altera/sdram_s10.c\n@@ -0,0 +1,382 @@\n+/*\n+ * Copyright (C) 2016-2017 Intel Corporation \n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0\n+ */\n+\n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+static const struct socfpga_ecc_hmc *socfpga_ecc_hmc_base =\n+\t\t(void *)SOCFPGA_SDR_ADDRESS;\n+static const struct socfpga_noc_ddr_scheduler *socfpga_noc_ddr_scheduler_base =\n+\t\t(void *)SOCFPGA_SDR_SCHEDULER_ADDRESS;\n+static const struct socfpga_io48_mmr *socfpga_io48_mmr_base =\n+\t\t(void *)SOCFPGA_HMC_MMR_IO48_ADDRESS;\n+static const struct socfpga_system_manager *sysmgr_regs =\n+\t\t(void *)SOCFPGA_SYSMGR_ADDRESS;\n+\n+#define DDR_CONFIG(A, B, C, R)\t((A<<24)|(B<<16)|(C<<8)|R)\n+\n+/* The followring are the supported configurations */\n+u32 ddr_config[] = {\n+\t/* DDR_CONFIG(Address order,Bank,Column,Row) */\n+\t/* List for DDR3 or LPDDR3 (pinout order > chip, row, bank, column) */\n+\tDDR_CONFIG(0, 3, 10, 12),\n+\tDDR_CONFIG(0, 3, 9, 13),\n+\tDDR_CONFIG(0, 3, 10, 13),\n+\tDDR_CONFIG(0, 3, 9, 14),\n+\tDDR_CONFIG(0, 3, 10, 14),\n+\tDDR_CONFIG(0, 3, 10, 15),\n+\tDDR_CONFIG(0, 3, 11, 14),\n+\tDDR_CONFIG(0, 3, 11, 15),\n+\tDDR_CONFIG(0, 3, 10, 16),\n+\tDDR_CONFIG(0, 3, 11, 16),\n+\tDDR_CONFIG(0, 3, 12, 15),\t/* 0xa */\n+\t/* List for DDR4 only (pinout order > chip, bank, row, column) */\n+\tDDR_CONFIG(1, 3, 10, 14),\n+\tDDR_CONFIG(1, 4, 10, 14),\n+\tDDR_CONFIG(1, 3, 10, 15),\n+\tDDR_CONFIG(1, 4, 10, 15),\n+\tDDR_CONFIG(1, 3, 10, 16),\n+\tDDR_CONFIG(1, 4, 10, 16),\n+\tDDR_CONFIG(1, 3, 10, 17),\n+\tDDR_CONFIG(1, 4, 10, 17),\n+};\n+\n+#define DDR_CONFIG_ELEMENTS\t(sizeof(ddr_config)/sizeof(u32))\n+\n+int match_ddr_conf(u32 ddr_conf)\n+{\n+\tint i;\n+\tfor (i = 0; i < DDR_CONFIG_ELEMENTS; i++) {\n+\t\tif (ddr_conf == ddr_config[i])\n+\t\t\treturn i;\n+\t}\n+\treturn 0;\n+}\n+\n+static int emif_clear(void)\n+{\n+\tu32 s2c, i;\n+\n+\twritel(0, &socfpga_ecc_hmc_base->rsthandshakectrl);\n+\ts2c = readl(&socfpga_ecc_hmc_base->rsthandshakestat) &\n+\t DDR_HMC_RSTHANDSHAKE_MASK;\n+\n+\tfor (i = 1000; (i > 0) && s2c; i--) {\n+\t\tWATCHDOG_RESET();\n+\t\tmdelay(1);\n+\t\ts2c = readl(&socfpga_ecc_hmc_base->rsthandshakestat) &\n+\t\t DDR_HMC_RSTHANDSHAKE_MASK;\n+\t}\n+\treturn !s2c;\n+}\n+\n+static int emif_reset(void)\n+{\n+\tu32 c2s, s2c, i;\n+\n+\tc2s = readl(&socfpga_ecc_hmc_base->rsthandshakectrl) &\n+\t DDR_HMC_RSTHANDSHAKE_MASK;\n+\ts2c = readl(&socfpga_ecc_hmc_base->rsthandshakestat) &\n+\t DDR_HMC_RSTHANDSHAKE_MASK;\n+\n+\tdebug(\"DDR: c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\\n\",\n+\t c2s, s2c, readl(&socfpga_io48_mmr_base->niosreserve0),\n+\t readl(&socfpga_io48_mmr_base->niosreserve1),\n+\t readl(&socfpga_io48_mmr_base->niosreserve2),\n+\t readl(&socfpga_io48_mmr_base->dramsts));\n+\n+\tif (s2c && emif_clear()) {\n+\t\tprintf(\"DDR: emif_clear() failed\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tputs(\"DDR: Triggerring emif_reset\\n\");\n+\twritel(DDR_HMC_CORE2SEQ_INT_REQ,\n+\t &socfpga_ecc_hmc_base->rsthandshakectrl);\n+\n+\tfor (i = 1000; i > 0; i--) {\n+\t\t/* if seq2core[3] = 0, we are good */\n+\t\tif (!(readl(&socfpga_ecc_hmc_base->rsthandshakestat) &\n+\t\t DDR_HMC_SEQ2CORE_INT_RESP_MASK))\n+\t\t\tbreak;\n+\t\tWATCHDOG_RESET();\n+\t\tmdelay(1);\n+\t}\n+\n+\tif (!i) {\n+\t\tprintf(\"DDR: failed to get ack from EMIF\\n\");\n+\t\treturn -2;\n+\t}\n+\n+\tif (emif_clear()) {\n+\t\tprintf(\"DDR: emif_clear() failed\\n\");\n+\t\treturn -3;\n+\t}\n+\n+\tprintf(\"DDR: emif_reset triggered successly\\n\");\n+\treturn 0;\n+}\n+\n+static int poll_hmc_clock_status(void)\n+{\n+\tu32 status, i;\n+\n+\tfor (i = 1000; i > 0; i--) {\n+\t\tstatus = readl(&sysmgr_regs->hmc_clk) &\n+\t\t\t SYSMGR_HMC_CLK_STATUS_MSK;\n+\t\tudelay(1);\n+\t\tif (status)\n+\t\t\tbreak;\n+\t\tWATCHDOG_RESET();\n+\t}\n+\treturn status;\n+}\n+\n+/**\n+ * sdram_mmr_init_full() - Function to initialize SDRAM MMR\n+ *\n+ * Initialize the SDRAM MMR.\n+ */\n+int sdram_mmr_init_full(unsigned int unused)\n+{\n+\tu32 update_value, io48_value, ddrioctl;\n+\tu32 i, j, cal_success;\n+\n+\t/* Enable access to DDR from CPU master */\n+\tclrbits_le32(CCU_CPU0_MPRT_ADBASE_DDRREG_ADDR, CCU_ADBASE_DI_MASK);\n+\tclrbits_le32(CCU_CPU0_MPRT_ADBASE_MEMSPACE0_ADDR, CCU_ADBASE_DI_MASK);\n+\tclrbits_le32(CCU_CPU0_MPRT_ADBASE_MEMSPACE1A_ADDR, CCU_ADBASE_DI_MASK);\n+\tclrbits_le32(CCU_CPU0_MPRT_ADBASE_MEMSPACE1B_ADDR, CCU_ADBASE_DI_MASK);\n+\tclrbits_le32(CCU_CPU0_MPRT_ADBASE_MEMSPACE1C_ADDR, CCU_ADBASE_DI_MASK);\n+\tclrbits_le32(CCU_CPU0_MPRT_ADBASE_MEMSPACE1D_ADDR, CCU_ADBASE_DI_MASK);\n+\tclrbits_le32(CCU_CPU0_MPRT_ADBASE_MEMSPACE1E_ADDR, CCU_ADBASE_DI_MASK);\n+\n+\t/* Enable access to DDR from IO master */\n+\tclrbits_le32(CCU_IOM_MPRT_ADBASE_MEMSPACE0_ADDR, CCU_ADBASE_DI_MASK);\n+\tclrbits_le32(CCU_IOM_MPRT_ADBASE_MEMSPACE1A_ADDR, CCU_ADBASE_DI_MASK);\n+\tclrbits_le32(CCU_IOM_MPRT_ADBASE_MEMSPACE1B_ADDR, CCU_ADBASE_DI_MASK);\n+\tclrbits_le32(CCU_IOM_MPRT_ADBASE_MEMSPACE1C_ADDR, CCU_ADBASE_DI_MASK);\n+\tclrbits_le32(CCU_IOM_MPRT_ADBASE_MEMSPACE1D_ADDR, CCU_ADBASE_DI_MASK);\n+\tclrbits_le32(CCU_IOM_MPRT_ADBASE_MEMSPACE1E_ADDR, CCU_ADBASE_DI_MASK);\n+\n+\t/* this enables nonsecure access to DDR */\n+\t/* mpuregion0addr_limit */\n+\twritel(0xFFFF0000, 0xF8020118);\n+\twritel(0x1F, 0xF802011c);\n+\n+\t/* nonmpuregion0addr_limit */\n+\twritel(0xFFFF0000, 0xF8020198);\n+\twritel(0x1F, 0xF802019C);\n+\n+\t/* Enable mpuregion0enable and nonmpuregion0enable */\n+\twritel(BIT(0) | BIT(8), 0xF8020100);\n+\n+\t/* Ensure HMC clock is running */\n+\tif (!poll_hmc_clock_status()) {\n+\t\tputs(\"DDR: Error as HMC clock not running\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\t/* release DDR scheduler from reset */\n+\tsocfpga_per_reset(SOCFPGA_RESET(SDR), 0);\n+\n+\t/* Try 3 times to do a calibration */\n+\tfor (i = 0; i < 3; i++) {\n+\t\tcal_success = readl(&socfpga_ecc_hmc_base->ddrcalstat) &\n+\t\t\t DDR_HMC_DDRCALSTAT_CAL_MSK;\n+\t\t/* A delay to wait for calibration bit to set */\n+\t\tfor (j = 0; (j < 1000) && !cal_success; j++) {\n+\t\t\tWATCHDOG_RESET();\n+\t\t\tmdelay(1);\n+\t\t\tcal_success = readl(&socfpga_ecc_hmc_base->ddrcalstat)\n+\t\t\t\t & DDR_HMC_DDRCALSTAT_CAL_MSK;\n+\t\t}\n+\n+\t\tif (cal_success)\n+\t\t\tbreak;\n+\t\telse\n+\t\t\temif_reset();\n+\t}\n+\n+\tif (!cal_success) {\n+\t\tputs(\"DDR: Error as SDRAM calibration failed\\n\");\n+\t\treturn -1;\n+\t}\n+\tputs(\"DDR: Calibration success\\n\");\n+\n+\tunion ctrlcfg0_reg ctrlcfg0 = (union ctrlcfg0_reg)\n+\t\t\t\treadl(&socfpga_io48_mmr_base->ctrlcfg0);\n+\tunion ctrlcfg1_reg ctrlcfg1 = (union ctrlcfg1_reg)\n+\t\t\t\treadl(&socfpga_io48_mmr_base->ctrlcfg1);\n+\tunion dramaddrw_reg dramaddrw = (union dramaddrw_reg)\n+\t\t\t\treadl(&socfpga_io48_mmr_base->dramaddrw);\n+\tunion dramtiming0_reg dramtim0 = (union dramtiming0_reg)\n+\t\t\t\treadl(&socfpga_io48_mmr_base->dramtiming0);\n+\tunion caltiming0_reg caltim0 = (union caltiming0_reg)\n+\t\t\t\treadl(&socfpga_io48_mmr_base->caltiming0);\n+\tunion caltiming1_reg caltim1 = (union caltiming1_reg)\n+\t\t\t\treadl(&socfpga_io48_mmr_base->caltiming1);\n+\tunion caltiming2_reg caltim2 = (union caltiming2_reg)\n+\t\t\t\treadl(&socfpga_io48_mmr_base->caltiming2);\n+\tunion caltiming3_reg caltim3 = (union caltiming3_reg)\n+\t\t\t\treadl(&socfpga_io48_mmr_base->caltiming3);\n+\tunion caltiming4_reg caltim4 = (union caltiming4_reg)\n+\t\t\t\treadl(&socfpga_io48_mmr_base->caltiming4);\n+\tunion caltiming9_reg caltim9 = (union caltiming9_reg)\n+\t\t\t\treadl(&socfpga_io48_mmr_base->caltiming9);\n+\n+\t/*\n+\t * Configure the DDR IO size [0xFFCFB008]\n+\t * niosreserve0: Used to indicate DDR width &\n+\t *\tbit[7:0] = Number of data bits (bit[6:5] 0x01=32bit, 0x10=64bit)\n+\t *\tbit[8] = 1 if user-mode OCT is present\n+\t *\tbit[9] = 1 if warm reset compiled into EMIF Cal Code\n+\t *\tbit[10] = 1 if warm reset is on during generation in EMIF Cal\n+\t * niosreserve1: IP ADCDS version encoded as 16 bit value\n+\t *\tbit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta,\n+\t *\t\t\t 3=EAP, 4-6 are reserved)\n+\t *\tbit[5:3] = Service Pack # (e.g. 1)\n+\t *\tbit[9:6] = Minor Release #\n+\t *\tbit[14:10] = Major Release #\n+\t */\n+\tupdate_value = readl(&socfpga_io48_mmr_base->niosreserve0);\n+\twritel(((update_value & 0xFF) >> 5), &socfpga_ecc_hmc_base->ddrioctrl);\n+\tddrioctl = readl(&socfpga_ecc_hmc_base->ddrioctrl);\n+\n+\t/* enable HPS interface to HMC */\n+\twritel(DDR_HMC_HPSINTFCSEL_ENABLE_MASK,\n+\t &socfpga_ecc_hmc_base->hpsintfcsel);\n+\n+\t/* Set the DDR Configuration */\n+\tio48_value = DDR_CONFIG(ctrlcfg1.cfg_addr_order,\n+\t\t\t\t(dramaddrw.cfg_bank_addr_width +\n+\t\t\t\t dramaddrw.cfg_bank_group_addr_width),\n+\t\t\t\tdramaddrw.cfg_col_addr_width,\n+\t\t\t\tdramaddrw.cfg_row_addr_width);\n+\n+\tupdate_value = match_ddr_conf(io48_value);\n+\tif (update_value)\n+\t\twritel(update_value,\n+\t\t &socfpga_noc_ddr_scheduler_base->main_scheduler_ddrconf);\n+\n+\t/* Configure HMC dramaddrw */\n+\twritel(readl(&socfpga_io48_mmr_base->dramaddrw),\n+\t &socfpga_ecc_hmc_base->dramaddrwidth);\n+\n+\t/*\n+\t * Configure DDR timing\n+\t * RDTOMISS = tRTP + tRP + tRCD - BL/2\n+\t * WRTOMISS = WL + tWR + tRP + tRCD and\n+\t * WL = RL + BL/2 + 2 - rd-to-wr ; tWR = 15ns so...\n+\t * First part of equation is in memory clock units so divide by 2\n+\t * for HMC clock units. 1066MHz is close to 1ns so use 15 directly.\n+\t * WRTOMISS = ((RL + BL/2 + 2 + tWR) >> 1)- rd-to-wr + tRP + tRCD\n+\t */\n+\tupdate_value = caltim2.cfg_rd_to_pch + caltim4.cfg_pch_to_valid +\n+\t\t caltim0.cfg_act_to_rdwr -\n+\t\t (ctrlcfg0.cfg_ctrl_burst_len >> 2);\n+\tio48_value = (((dramtim0.cfg_tcl + 2 + DDR_TWR +\n+\t\t (ctrlcfg0.cfg_ctrl_burst_len >> 1)) >> 1) -\n+\t\t /* Up to here was in memory cycles so divide by 2 */\n+\t\t caltim1.cfg_rd_to_wr + caltim0.cfg_act_to_rdwr +\n+\t\t caltim4.cfg_pch_to_valid);\n+\n+\twritel(((caltim0.cfg_act_to_act << DDR_SCHED_DDRTIMING_ACTTOACT_OFFSET) |\n+\t\t(update_value << DDR_SCHED_DDRTIMING_RDTOMISS_OFFSET) |\n+\t\t(io48_value << DDR_SCHED_DDRTIMING_WRTOMISS_OFFSET) |\n+\t\t((ctrlcfg0.cfg_ctrl_burst_len >> 2) <<\n+\t\t\tDDR_SCHED_DDRTIMING_BURSTLEN_OFFSET) |\n+\t\t(caltim1.cfg_rd_to_wr << DDR_SCHED_DDRTIMING_RDTOWR_OFFSET) |\n+\t\t(caltim3.cfg_wr_to_rd << DDR_SCHED_DDRTIMING_WRTORD_OFFSET) |\n+\t\t(((ddrioctl == 1) ? 1 : 0) <<\n+\t\t\tDDR_SCHED_DDRTIMING_BWRATIO_OFFSET)),\n+\t\t&socfpga_noc_ddr_scheduler_base->main_scheduler_ddrtiming);\n+\n+\t/* Configure DDR mode [precharge = 0] */\n+\twritel(((ddrioctl ? 0 : 1) << DDR_SCHED_DDRMOD_BWRATIOEXTENDED_OFFSET),\n+\t &socfpga_noc_ddr_scheduler_base->main_scheduler_ddrmode);\n+\n+\t/* Configure the read latency */\n+\twritel((dramtim0.cfg_tcl >> 1) + DDR_READ_LATENCY_DELAY,\n+\t &socfpga_noc_ddr_scheduler_base->main_scheduler_readlatency);\n+\n+\t/*\n+\t * Configuring timing values concerning activate commands\n+\t * [FAWBANK alway 1 because always 4 bank DDR]\n+\t */\n+\twritel(((caltim0.cfg_act_to_act_db << DDR_SCHED_ACTIVATE_RRD_OFFSET) |\n+\t (caltim9.cfg_4_act_to_act << DDR_SCHED_ACTIVATE_FAW_OFFSET) |\n+\t (DDR_ACTIVATE_FAWBANK << DDR_SCHED_ACTIVATE_FAWBANK_OFFSET)),\n+\t &socfpga_noc_ddr_scheduler_base->main_scheduler_activate);\n+\n+\t/*\n+\t * Configuring timing values concerning device to device data bus\n+\t * ownership change\n+\t */\n+\twritel(((caltim1.cfg_rd_to_rd_dc <<\n+\t\t\tDDR_SCHED_DEVTODEV_BUSRDTORD_OFFSET) |\n+\t (caltim1.cfg_rd_to_wr_dc <<\n+\t\t\tDDR_SCHED_DEVTODEV_BUSRDTOWR_OFFSET) |\n+\t (caltim3.cfg_wr_to_rd_dc <<\n+\t\t\tDDR_SCHED_DEVTODEV_BUSWRTORD_OFFSET)),\n+\t &socfpga_noc_ddr_scheduler_base->main_scheduler_devtodev);\n+\n+\t/* Enable or disable the SDRAM ECC */\n+\tif (ctrlcfg1.cfg_ctrl_enable_ecc) {\n+\t\tsetbits_le32(&socfpga_ecc_hmc_base->eccctrl,\n+\t\t\t (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |\n+\t\t\t DDR_HMC_ECCCTL_CNT_RST_SET_MSK |\n+\t\t\t DDR_HMC_ECCCTL_ECC_EN_SET_MSK));\n+\t\tclrbits_le32(&socfpga_ecc_hmc_base->eccctrl,\n+\t\t\t (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |\n+\t\t\t DDR_HMC_ECCCTL_CNT_RST_SET_MSK));\n+\t\tsetbits_le32(&socfpga_ecc_hmc_base->eccctrl2,\n+\t\t\t (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |\n+\t\t\t DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));\n+\t} else {\n+\t\tclrbits_le32(&socfpga_ecc_hmc_base->eccctrl,\n+\t\t\t (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |\n+\t\t\t DDR_HMC_ECCCTL_CNT_RST_SET_MSK |\n+\t\t\t DDR_HMC_ECCCTL_ECC_EN_SET_MSK));\n+\t\tclrbits_le32(&socfpga_ecc_hmc_base->eccctrl2,\n+\t\t\t (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |\n+\t\t\t DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));\n+\t}\n+\n+\tputs(\"DDR: HMC init success\\n\");\n+\treturn 0;\n+}\n+\n+/**\n+ * sdram_calculate_size() - Calculate SDRAM size\n+ *\n+ * Calculate SDRAM device size based on SDRAM controller parameters.\n+ * Size is specified in bytes.\n+ */\n+unsigned long sdram_calculate_size(void)\n+{\n+\tunion dramaddrw_reg dramaddrw =\n+\t\t(union dramaddrw_reg)readl(&socfpga_io48_mmr_base->dramaddrw);\n+\n+\tu32 size = (1 << (dramaddrw.cfg_cs_addr_width +\n+\t\t dramaddrw.cfg_bank_group_addr_width +\n+\t\t dramaddrw.cfg_bank_addr_width +\n+\t\t dramaddrw.cfg_row_addr_width +\n+\t\t dramaddrw.cfg_col_addr_width));\n+\n+\tsize *= (2 << (readl(&socfpga_ecc_hmc_base->ddrioctrl) &\n+\t\t DDR_HMC_DDRIOCTRL_IOSIZE_MSK));\n+\n+\treturn size;\n+}\n","prefixes":["U-Boot","12/14"]}