{"id":815370,"url":"http://patchwork.ozlabs.org/api/patches/815370/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1505812951-25088-9-git-send-email-chin.liang.see@intel.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1505812951-25088-9-git-send-email-chin.liang.see@intel.com>","list_archive_url":null,"date":"2017-09-19T09:22:25","name":"[U-Boot,08/14] arm: socfpga: stratix10: Add MMU support for Stratix10 SoC","commit_ref":null,"pull_url":null,"state":"superseded","archived":false,"hash":"a2777d8767df5d320af738974094c288494a7e86","submitter":{"id":70182,"url":"http://patchwork.ozlabs.org/api/people/70182/?format=json","name":"See, Chin Liang","email":"chin.liang.see@intel.com"},"delegate":{"id":1699,"url":"http://patchwork.ozlabs.org/api/users/1699/?format=json","username":"marex","first_name":"Marek","last_name":"Vasut","email":"marek.vasut@gmail.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1505812951-25088-9-git-send-email-chin.liang.see@intel.com/mbox/","series":[{"id":3810,"url":"http://patchwork.ozlabs.org/api/series/3810/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=3810","date":"2017-09-19T09:22:17","name":"Enable Stratix10 SoC support","version":1,"mbox":"http://patchwork.ozlabs.org/series/3810/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/815370/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/815370/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xxHhz4dpJz9s78\n\tfor ;\n\tTue, 19 Sep 2017 19:32:35 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 59CB4C21F0E; Tue, 19 Sep 2017 09:28:38 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 30449C21DD1;\n\tTue, 19 Sep 2017 09:24:47 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid E67FBC21F0B; Tue, 19 Sep 2017 09:23:38 +0000 (UTC)","from mga14.intel.com (mga14.intel.com [192.55.52.115])\n\tby lists.denx.de (Postfix) with ESMTPS id 2A0A3C21EF1\n\tfor ; Tue, 19 Sep 2017 09:23:31 +0000 (UTC)","from fmsmga002.fm.intel.com ([10.253.24.26])\n\tby fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t19 Sep 2017 02:23:30 -0700","from pg-interactive1.altera.com ([137.57.137.156])\n\tby fmsmga002.fm.intel.com with ESMTP; 19 Sep 2017 02:22:54 -0700"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-5.0 required=5.0 tests=RCVD_IN_DNSWL_HI\n\tautolearn=unavailable autolearn_force=no version=3.4.0","X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos; i=\"5.42,417,1500966000\"; d=\"scan'208\";\n\ta=\"1220782315\"","From":"chin.liang.see@intel.com","To":"u-boot@lists.denx.de,\n\tMarek Vasut ","Date":"Tue, 19 Sep 2017 17:22:25 +0800","Message-Id":"<1505812951-25088-9-git-send-email-chin.liang.see@intel.com>","X-Mailer":"git-send-email 2.2.2","In-Reply-To":"<1505812951-25088-1-git-send-email-chin.liang.see@intel.com>","References":"<1505812951-25088-1-git-send-email-chin.liang.see@intel.com>","Cc":"Tien Fong Chee ,\n\tChin Liang See ","Subject":"[U-Boot] [PATCH 08/14] arm: socfpga: stratix10: Add MMU support for\n\tStratix10 SoC","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"From: Chin Liang See \n\nAdd MMU support for Stratix SoC\n\nSigned-off-by: Chin Liang See \n---\n arch/arm/mach-socfpga/Makefile | 1 +\n arch/arm/mach-socfpga/mmu-arm64_s10.c | 71 +++++++++++++++++++++++++++++++++++\n 2 files changed, 72 insertions(+)\n create mode 100644 arch/arm/mach-socfpga/mmu-arm64_s10.c","diff":"diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile\nindex 43e18d2..098e5e9 100644\n--- a/arch/arm/mach-socfpga/Makefile\n+++ b/arch/arm/mach-socfpga/Makefile\n@@ -34,6 +34,7 @@ ifdef CONFIG_TARGET_SOCFPGA_STRATIX10\n obj-y\t+= clock_manager_s10.o\n obj-y\t+= mailbox_s10.o\n obj-y\t+= misc_s10.o\n+obj-y\t+= mmu-arm64_s10.o\n obj-y\t+= reset_manager_s10.o\n obj-y\t+= system_manager_s10.o\n obj-y\t+= wrap_pinmux_config_s10.o\ndiff --git a/arch/arm/mach-socfpga/mmu-arm64_s10.c b/arch/arm/mach-socfpga/mmu-arm64_s10.c\nnew file mode 100644\nindex 0000000..91c7f2e\n--- /dev/null\n+++ b/arch/arm/mach-socfpga/mmu-arm64_s10.c\n@@ -0,0 +1,71 @@\n+/*\n+ * Copyright (C) 2016-2017 Intel Corporation \n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0\n+ */\n+\n+#include \n+#include \n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+static struct mm_region socfpga_stratix10_mem_map[] = {\n+\t{\n+\t\t/* MEM 2GB*/\n+\t\t.virt\t= 0x0UL,\n+\t\t.phys\t= 0x0UL,\n+\t\t.size\t= 0x80000000UL,\n+\t\t.attrs\t= PTE_BLOCK_MEMTYPE(MT_NORMAL) |\n+\t\t\t\tPTE_BLOCK_INNER_SHARE,\n+\t}, {\n+\t\t/* FPGA 1.5GB */\n+\t\t.virt\t= 0x80000000UL,\n+\t\t.phys\t= 0x80000000UL,\n+\t\t.size\t= 0x60000000UL,\n+\t\t.attrs\t= PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |\n+\t\t\t\tPTE_BLOCK_NON_SHARE |\n+\t\t\t\tPTE_BLOCK_PXN | PTE_BLOCK_UXN,\n+\t}, {\n+\t\t/* DEVICE 142MB */\n+\t\t.virt\t= 0xF7000000UL,\n+\t\t.phys\t= 0xF7000000UL,\n+\t\t.size\t= 0x08E00000UL,\n+\t\t.attrs\t= PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |\n+\t\t\t\tPTE_BLOCK_NON_SHARE |\n+\t\t\t\tPTE_BLOCK_PXN | PTE_BLOCK_UXN,\n+\t}, {\n+\t\t/* OCRAM 1MB but available 256KB */\n+\t\t.virt\t= 0xFFE00000UL,\n+\t\t.phys\t= 0xFFE00000UL,\n+\t\t.size\t= 0x00100000UL,\n+\t\t.attrs\t= PTE_BLOCK_MEMTYPE(MT_NORMAL) |\n+\t\t\t\tPTE_BLOCK_INNER_SHARE,\n+\t}, {\n+\t\t/* DEVICE 32KB */\n+\t\t.virt\t= 0xFFFC0000UL,\n+\t\t.phys\t= 0xFFFC0000UL,\n+\t\t.size\t= 0x00008000UL,\n+\t\t.attrs\t= PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |\n+\t\t\t\tPTE_BLOCK_NON_SHARE |\n+\t\t\t\tPTE_BLOCK_PXN | PTE_BLOCK_UXN,\n+\t}, {\n+\t\t/* MEM 124GB */\n+\t\t.virt\t= 0x0100000000UL,\n+\t\t.phys\t= 0x0100000000UL,\n+\t\t.size\t= 0x1F00000000UL,\n+\t\t.attrs\t= PTE_BLOCK_MEMTYPE(MT_NORMAL) |\n+\t\t\t\tPTE_BLOCK_INNER_SHARE,\n+\t}, {\n+\t\t/* DEVICE 4GB */\n+\t\t.virt\t= 0x2000000000UL,\n+\t\t.phys\t= 0x2000000000UL,\n+\t\t.size\t= 0x0100000000UL,\n+\t\t.attrs\t= PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |\n+\t\t\t\tPTE_BLOCK_NON_SHARE |\n+\t\t\t\tPTE_BLOCK_PXN | PTE_BLOCK_UXN,\n+\t}, {\n+\t\t/* List terminator */\n+\t},\n+};\n+\n+struct mm_region *mem_map = socfpga_stratix10_mem_map;\n","prefixes":["U-Boot","08/14"]}