{"id":815369,"url":"http://patchwork.ozlabs.org/api/patches/815369/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1505812951-25088-12-git-send-email-chin.liang.see@intel.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1505812951-25088-12-git-send-email-chin.liang.see@intel.com>","list_archive_url":null,"date":"2017-09-19T09:22:28","name":"[U-Boot,11/14] arm: socfpga: stratix10: Add timer support for Stratix10 SoC","commit_ref":null,"pull_url":null,"state":"superseded","archived":false,"hash":"e13a3ba25fde9d8b24fdc296f24e19f5255bf898","submitter":{"id":70182,"url":"http://patchwork.ozlabs.org/api/people/70182/?format=json","name":"See, Chin Liang","email":"chin.liang.see@intel.com"},"delegate":{"id":1699,"url":"http://patchwork.ozlabs.org/api/users/1699/?format=json","username":"marex","first_name":"Marek","last_name":"Vasut","email":"marek.vasut@gmail.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1505812951-25088-12-git-send-email-chin.liang.see@intel.com/mbox/","series":[{"id":3810,"url":"http://patchwork.ozlabs.org/api/series/3810/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=3810","date":"2017-09-19T09:22:17","name":"Enable Stratix10 SoC support","version":1,"mbox":"http://patchwork.ozlabs.org/series/3810/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/815369/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/815369/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xxHhd1qXGz9s78\n\tfor ;\n\tTue, 19 Sep 2017 19:32:17 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 0F14FC21F01; Tue, 19 Sep 2017 09:27:55 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 06682C21EFD;\n\tTue, 19 Sep 2017 09:24:32 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 8EEAEC21DD1; Tue, 19 Sep 2017 09:23:39 +0000 (UTC)","from mga14.intel.com (mga14.intel.com [192.55.52.115])\n\tby lists.denx.de (Postfix) with ESMTPS id 2F3D8C21EEA\n\tfor ; Tue, 19 Sep 2017 09:23:33 +0000 (UTC)","from fmsmga002.fm.intel.com ([10.253.24.26])\n\tby fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t19 Sep 2017 02:23:31 -0700","from pg-interactive1.altera.com ([137.57.137.156])\n\tby fmsmga002.fm.intel.com with ESMTP; 19 Sep 2017 02:23:00 -0700"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-5.0 required=5.0 tests=RCVD_IN_DNSWL_HI\n\tautolearn=unavailable autolearn_force=no version=3.4.0","X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos; i=\"5.42,417,1500966000\"; d=\"scan'208\";\n\ta=\"1220782344\"","From":"chin.liang.see@intel.com","To":"u-boot@lists.denx.de,\n\tMarek Vasut ","Date":"Tue, 19 Sep 2017 17:22:28 +0800","Message-Id":"<1505812951-25088-12-git-send-email-chin.liang.see@intel.com>","X-Mailer":"git-send-email 2.2.2","In-Reply-To":"<1505812951-25088-1-git-send-email-chin.liang.see@intel.com>","References":"<1505812951-25088-1-git-send-email-chin.liang.see@intel.com>","Cc":"Tien Fong Chee ,\n\tChin Liang See ","Subject":"[U-Boot] [PATCH 11/14] arm: socfpga: stratix10: Add timer support\n\tfor Stratix10 SoC","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"From: Chin Liang See \n\nAdd timer support for Stratix SoC\n\nSigned-off-by: Chin Liang See \n---\n arch/arm/mach-socfpga/timer.c | 17 ++++++++++++++++-\n 1 file changed, 16 insertions(+), 1 deletion(-)","diff":"diff --git a/arch/arm/mach-socfpga/timer.c b/arch/arm/mach-socfpga/timer.c\nindex 253cde3..23450b0 100644\n--- a/arch/arm/mach-socfpga/timer.c\n+++ b/arch/arm/mach-socfpga/timer.c\n@@ -1,5 +1,6 @@\n /*\n- * Copyright (C) 2012 Altera Corporation \n+ * Copyright (C) 2016-2017 Intel Corporation \n+ * Copyright (C) 2012-2016 Altera Corporation \n *\n * SPDX-License-Identifier:\tGPL-2.0+\n */\n@@ -10,15 +11,29 @@\n \n #define TIMER_LOAD_VAL\t\t0xFFFFFFFF\n \n+#if !defined(CONFIG_TARGET_SOCFPGA_STRATIX10)\n static const struct socfpga_timer *timer_base = (void *)CONFIG_SYS_TIMERBASE;\n+#endif\n \n /*\n * Timer initialization\n */\n int timer_init(void)\n {\n+#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)\n+\tint enable = 0x3;\t/* timer enable + output signal masked */\n+\tint loadval = ~0;\n+\n+\t/* enable system counter */\n+\twritel(enable, SOCFPGA_GTIMER_SEC_ADDRESS);\n+\t/* enable processor pysical counter */\n+\tasm volatile(\"msr cntp_ctl_el0, %0\" : : \"r\" (enable));\n+\tasm volatile(\"msr cntp_tval_el0, %0\" : : \"r\" (loadval));\n+\n+#else\n \twritel(TIMER_LOAD_VAL, &timer_base->load_val);\n \twritel(TIMER_LOAD_VAL, &timer_base->curr_val);\n \twritel(readl(&timer_base->ctrl) | 0x3, &timer_base->ctrl);\n+#endif\n \treturn 0;\n }\n","prefixes":["U-Boot","11/14"]}