{"id":815366,"url":"http://patchwork.ozlabs.org/api/patches/815366/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1505812951-25088-11-git-send-email-chin.liang.see@intel.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1505812951-25088-11-git-send-email-chin.liang.see@intel.com>","list_archive_url":null,"date":"2017-09-19T09:22:27","name":"[U-Boot,10/14] arm: socfpga: stratix10: Add SPL driver for Stratix10 SoC","commit_ref":null,"pull_url":null,"state":"superseded","archived":false,"hash":"bc9f40847c1f62d853bf277f36a17dcc365c5cd5","submitter":{"id":70182,"url":"http://patchwork.ozlabs.org/api/people/70182/?format=json","name":"See, Chin Liang","email":"chin.liang.see@intel.com"},"delegate":{"id":1699,"url":"http://patchwork.ozlabs.org/api/users/1699/?format=json","username":"marex","first_name":"Marek","last_name":"Vasut","email":"marek.vasut@gmail.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1505812951-25088-11-git-send-email-chin.liang.see@intel.com/mbox/","series":[{"id":3810,"url":"http://patchwork.ozlabs.org/api/series/3810/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=3810","date":"2017-09-19T09:22:17","name":"Enable Stratix10 SoC support","version":1,"mbox":"http://patchwork.ozlabs.org/series/3810/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/815366/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/815366/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xxHfL4XrGz9sMN\n\tfor ;\n\tTue, 19 Sep 2017 19:30:18 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 68C7CC21EF4; Tue, 19 Sep 2017 09:26:28 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 2B295C21F02;\n\tTue, 19 Sep 2017 09:24:11 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 816DEC21EDB; Tue, 19 Sep 2017 09:23:38 +0000 (UTC)","from mga14.intel.com (mga14.intel.com [192.55.52.115])\n\tby lists.denx.de (Postfix) with ESMTPS id 2E5CBC21E27\n\tfor ; Tue, 19 Sep 2017 09:23:33 +0000 (UTC)","from fmsmga002.fm.intel.com ([10.253.24.26])\n\tby fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t19 Sep 2017 02:23:30 -0700","from pg-interactive1.altera.com ([137.57.137.156])\n\tby fmsmga002.fm.intel.com with ESMTP; 19 Sep 2017 02:22:58 -0700"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-5.0 required=5.0 tests=RCVD_IN_DNSWL_HI\n\tautolearn=unavailable autolearn_force=no version=3.4.0","X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos; i=\"5.42,417,1500966000\"; d=\"scan'208\";\n\ta=\"1220782336\"","From":"chin.liang.see@intel.com","To":"u-boot@lists.denx.de,\n\tMarek Vasut ","Date":"Tue, 19 Sep 2017 17:22:27 +0800","Message-Id":"<1505812951-25088-11-git-send-email-chin.liang.see@intel.com>","X-Mailer":"git-send-email 2.2.2","In-Reply-To":"<1505812951-25088-1-git-send-email-chin.liang.see@intel.com>","References":"<1505812951-25088-1-git-send-email-chin.liang.see@intel.com>","Cc":"Tien Fong Chee ,\n\tChin Liang See ","Subject":"[U-Boot] [PATCH 10/14] arm: socfpga: stratix10: Add SPL driver for\n\tStratix10 SoC","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"From: Chin Liang See \n\nAdd SPL driver support for Stratix SoC\n\nSigned-off-by: Chin Liang See \n---\n arch/arm/mach-socfpga/Makefile | 4 +\n arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 4 +\n arch/arm/mach-socfpga/include/mach/firewall_s10.h | 84 +++++++++++++\n arch/arm/mach-socfpga/spl_s10.c | 138 +++++++++++++++++++++\n 4 files changed, 230 insertions(+)\n create mode 100644 arch/arm/mach-socfpga/include/mach/firewall_s10.h\n create mode 100644 arch/arm/mach-socfpga/spl_s10.c","diff":"diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile\nindex b669d43..35b124a 100644\n--- a/arch/arm/mach-socfpga/Makefile\n+++ b/arch/arm/mach-socfpga/Makefile\n@@ -40,6 +40,7 @@ obj-y\t+= system_manager_s10.o\n obj-y\t+= wrap_pinmux_config_s10.o\n obj-y\t+= wrap_pll_config_s10.o\n endif\n+\n ifdef CONFIG_SPL_BUILD\n ifdef CONFIG_TARGET_SOCFPGA_GEN5\n obj-y\t+= spl_gen5.o\n@@ -51,6 +52,9 @@ endif\n ifdef CONFIG_TARGET_SOCFPGA_ARRIA10\n obj-y\t+= spl_a10.o\n endif\n+ifdef CONFIG_TARGET_SOCFPGA_STRATIX10\n+obj-y\t+= spl_s10.o\n+endif\n endif\n \n ifdef CONFIG_TARGET_SOCFPGA_GEN5\ndiff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h\nindex feb1881..d79b9cd 100644\n--- a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h\n+++ b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h\n@@ -45,6 +45,10 @@\n #define SOCFPGA_RSTMGR_ADDRESS\t\t\t0xffd11000\n #define SOCFPGA_SYSMGR_ADDRESS\t\t\t0xffd12000\n #define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS\t0xffd13000\n+#define SOCFPGA_FIREWALL_L4_PER\t\t\t0xffd21000\n+#define SOCFPGA_FIREWALL_L4_SYS\t\t\t0xffd21100\n+#define SOCFPGA_FIREWALL_SOC2FPGA\t\t0xffd21200\n+#define SOCFPGA_FIREWALL_LWSOC2FPGA\t\t0xffd21300\n #define SOCFPGA_DMANONSECURE_ADDRESS\t\t0xffda0000\n #define SOCFPGA_DMASECURE_ADDRESS\t\t0xffda1000\n #define SOCFPGA_SPIS0_ADDRESS\t\t\t0xffda2000\ndiff --git a/arch/arm/mach-socfpga/include/mach/firewall_s10.h b/arch/arm/mach-socfpga/include/mach/firewall_s10.h\nnew file mode 100644\nindex 0000000..6894bb9\n--- /dev/null\n+++ b/arch/arm/mach-socfpga/include/mach/firewall_s10.h\n@@ -0,0 +1,84 @@\n+/*\n+ * Copyright (C) 2017 Intel Corporation \n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0\n+ */\n+\n+#ifndef\t_FIREWALL_S10_\n+#define\t_FIREWALL_S10_\n+\n+struct socfpga_firwall_l4_per {\n+\tu32\tnand;\t\t/* 0x00 */\n+\tu32\tnand_data;\n+\tu32\t_pad_0x8;\n+\tu32\tusb0;\n+\tu32\tusb1;\t\t/* 0x10 */\n+\tu32\t_pad_0x14;\n+\tu32\t_pad_0x18;\n+\tu32\tspim0;\n+\tu32\tspim1;\t\t/* 0x20 */\n+\tu32\tspis0;\n+\tu32\tspis1;\n+\tu32\temac0;\n+\tu32\temac1;\t\t/* 0x30 */\n+\tu32\temac2;\n+\tu32\t_pad_0x38;\n+\tu32\t_pad_0x3c;\n+\tu32\tsdmmc;\t\t/* 0x40 */\n+\tu32\tgpio0;\n+\tu32\tgpio1;\n+\tu32\t_pad_0x4c;\n+\tu32\ti2c0;\t\t/* 0x50 */\n+\tu32\ti2c1;\n+\tu32\ti2c2;\n+\tu32\ti2c3;\n+\tu32\ti2c4;\t\t/* 0x60 */\n+\tu32\ttimer0;\n+\tu32\ttimer1;\n+\tu32\tuart0;\n+\tu32\tuart1;\t\t/* 0x70 */\n+};\n+\n+struct socfpga_firwall_l4_sys {\n+\tu32\t_pad_0x00;\t\t/* 0x00 */\n+\tu32\t_pad_0x04;\n+\tu32\tdma_ecc;\n+\tu32\temac0rx_ecc;\n+\tu32\temac0tx_ecc;\t\t/* 0x10 */\n+\tu32\temac1rx_ecc;\n+\tu32\temac1tx_ecc;\n+\tu32\temac2rx_ecc;\n+\tu32\temac2tx_ecc;\t\t/* 0x20 */\n+\tu32\t_pad_0x24;\n+\tu32\t_pad_0x28;\n+\tu32\tnand_ecc;\n+\tu32\tnand_read_ecc;\t\t/* 0x30 */\n+\tu32\tnand_write_ecc;\n+\tu32\tocram_ecc;\n+\tu32\t_pad_0x3c;\n+\tu32\tsdmmc_ecc;\t\t/* 0x40 */\n+\tu32\tusb0_ecc;\n+\tu32\tusb1_ecc;\n+\tu32\tclock_manager;\n+\tu32\t_pad_0x50;\t\t/* 0x50 */\n+\tu32\tio_manager;\n+\tu32\treset_manager;\n+\tu32\tsystem_manager;\n+\tu32\tosc0_timer;\t\t/* 0x60 */\n+\tu32\tosc1_timer;\n+\tu32\twatchdog0;\n+\tu32\twatchdog1;\n+\tu32\twatchdog2;\t\t/* 0x70 */\n+\tu32\twatchdog3;\n+};\n+\n+#define FIREWALL_L4_DISABLE_ALL\t\t(BIT(0) | BIT(24) | BIT(16))\n+#define FIREWALL_BRIDGE_DISABLE_ALL\t(~0)\n+\n+#define CCU_CPU0_MPRT_ADMASK_MEM_RAM0_ADDR\t0xf7004688\n+#define CCU_IOM_MPRT_ADMASK_MEM_RAM0_ADDR\t0xf7018628\n+\n+#define CCU_ADMASK_P_MASK\t\t\t(BIT(0))\n+#define CCU_ADMASK_NS_MASK\t\t\t(BIT(1))\n+\n+#endif /* _FIREWALL_S10_ */\ndiff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c\nnew file mode 100644\nindex 0000000..12cafe6\n--- /dev/null\n+++ b/arch/arm/mach-socfpga/spl_s10.c\n@@ -0,0 +1,138 @@\n+/*\n+ * Copyright (C) 2016-2017 Intel Corporation \n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0\n+ */\n+\n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+static const struct socfpga_firwall_l4_per *firwall_l4_per_base =\n+\t(struct socfpga_firwall_l4_per *)SOCFPGA_FIREWALL_L4_PER;\n+static const struct socfpga_firwall_l4_sys *firwall_l4_sys_base =\n+\t(struct socfpga_firwall_l4_sys *)SOCFPGA_FIREWALL_L4_SYS;\n+\n+u32 spl_boot_device(void)\n+{\n+\t/* TODO: Get from SDM or handoff */\n+/* #ifdef CONFIG_CADENCE_QSPI*/\n+#if 0\n+\treturn BOOT_DEVICE_SPI;\n+#else\n+\treturn BOOT_DEVICE_MMC1;\n+#endif\n+}\n+\n+#ifdef CONFIG_SPL_MMC_SUPPORT\n+u32 spl_boot_mode(const u32 boot_device)\n+{\n+#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)\n+\treturn MMCSD_MODE_FS;\n+#else\n+\treturn MMCSD_MODE_RAW;\n+#endif\n+}\n+#endif\n+\n+void board_init_f(ulong dummy)\n+{\n+\tconst struct cm_config *cm_default_cfg = cm_get_default_config();\n+\n+\tsocfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);\n+\ttimer_init();\n+\n+\tpopulate_sysmgr_pinmux();\n+\n+\t/* configuring the HPS clocks */\n+\tcm_basic_init(cm_default_cfg);\n+\n+\t/* enable console uart printing */\n+#if (CONFIG_SYS_NS16550_COM1 == SOCFPGA_UART0_ADDRESS)\n+\tsocfpga_per_reset(SOCFPGA_RESET(UART0), 0);\n+\t/* enables nonsecure access to UART0 */\n+\twritel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->uart0);\n+#elif (CONFIG_SYS_NS16550_COM1 == SOCFPGA_UART1_ADDRESS)\n+\tsocfpga_per_reset(SOCFPGA_RESET(UART1), 0);\n+\t/* enables nonsecure access to UART1 */\n+\twritel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->uart1);\n+#endif\n+\n+\tpreloader_console_init();\n+\tcm_print_clock_quick_summary();\n+\n+\t/* enable all EMACs */\n+\twritel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->emac0);\n+\twritel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->emac1);\n+\twritel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->emac2);\n+\t/* enables nonsecure access to all the emacs */\n+\twritel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->emac0rx_ecc);\n+\twritel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->emac0tx_ecc);\n+\twritel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->emac1rx_ecc);\n+\twritel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->emac1tx_ecc);\n+\twritel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->emac2rx_ecc);\n+\twritel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->emac2tx_ecc);\n+\n+\t/* enables SDMMC */\n+\tsocfpga_per_reset(SOCFPGA_RESET(SDMMC_OCP), 0);\n+\tsocfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);\n+\t/* Enables nonsecure access to SDMMC */\n+\twritel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->sdmmc);\n+\twritel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->sdmmc_ecc);\n+\n+\t/* enable i2c0 and i2c1 */\n+\tsocfpga_per_reset(SOCFPGA_RESET(I2C0), 0);\n+\tsocfpga_per_reset(SOCFPGA_RESET(I2C1), 0);\n+\t/* enables nonsecure access to i2c0 and i2c1 */\n+\twritel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->i2c0);\n+\twritel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->i2c1);\n+\n+\t/* disable lwsocf2fpga and soc2fpga bridge security */\n+\twritel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_SOC2FPGA);\n+\twritel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_LWSOC2FPGA);\n+\n+\t/* enables nonsecure access to clock mgr */\n+\twritel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->clock_manager);\n+\n+\t/* enables nonsecure access to OCRAM */\n+\twritel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->ocram_ecc);\n+\n+\t/* disable ocram security at CCU for non secure access */\n+\tclrbits_le32(CCU_CPU0_MPRT_ADMASK_MEM_RAM0_ADDR,\n+\t\t CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);\n+\tclrbits_le32(CCU_IOM_MPRT_ADMASK_MEM_RAM0_ADDR,\n+\t\t CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);\n+\n+\tputs(\"DDR: Initializing Hard Memory Controller\\n\");\n+\tif (sdram_mmr_init_full(0)) {\n+\t\tputs(\"DDR: Initialization failed.\\n\");\n+\t\thang();\n+\t}\n+\n+\tgd->ram_size = sdram_calculate_size();\n+\tprintf(\"DDR: %d MiB\\n\", (int)(gd->ram_size >> 20));\n+\n+\t/* Sanity check ensure correct SDRAM size specified */\n+\tputs(\"DDR: Running SDRAM size sanity check\\n\");\n+\tif (get_ram_size(0, gd->ram_size) != gd->ram_size) {\n+\t\tputs(\"DDR: SDRAM size check failed!\\n\");\n+\t\thang();\n+\t}\n+\tputs(\"DDR: SDRAM size check passed!\\n\");\n+\n+#ifdef CONFIG_CADENCE_QSPI\n+\tmbox_init();\n+\tmbox_qspi_open();\n+#endif\n+}\n","prefixes":["U-Boot","10/14"]}