{"id":815365,"url":"http://patchwork.ozlabs.org/api/patches/815365/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1505812951-25088-4-git-send-email-chin.liang.see@intel.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1505812951-25088-4-git-send-email-chin.liang.see@intel.com>","list_archive_url":null,"date":"2017-09-19T09:22:20","name":"[U-Boot,03/14] arm: socfpga: stratix10: Add Clock Manager driver for Stratix10 SoC","commit_ref":null,"pull_url":null,"state":"superseded","archived":false,"hash":"db0211777e9c391f695124f210669d76673359dc","submitter":{"id":70182,"url":"http://patchwork.ozlabs.org/api/people/70182/?format=json","name":"See, Chin Liang","email":"chin.liang.see@intel.com"},"delegate":{"id":1699,"url":"http://patchwork.ozlabs.org/api/users/1699/?format=json","username":"marex","first_name":"Marek","last_name":"Vasut","email":"marek.vasut@gmail.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1505812951-25088-4-git-send-email-chin.liang.see@intel.com/mbox/","series":[{"id":3810,"url":"http://patchwork.ozlabs.org/api/series/3810/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=3810","date":"2017-09-19T09:22:17","name":"Enable Stratix10 SoC support","version":1,"mbox":"http://patchwork.ozlabs.org/series/3810/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/815365/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/815365/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xxHdk6TpWz9s78\n\tfor ;\n\tTue, 19 Sep 2017 19:29:46 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 94748C21EED; Tue, 19 Sep 2017 09:24:55 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 08441C21EE1;\n\tTue, 19 Sep 2017 09:23:32 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 702A3C21EE1; Tue, 19 Sep 2017 09:23:24 +0000 (UTC)","from mga03.intel.com (mga03.intel.com [134.134.136.65])\n\tby lists.denx.de (Postfix) with ESMTPS id 0D1F5C21E3E\n\tfor ; Tue, 19 Sep 2017 09:23:19 +0000 (UTC)","from fmsmga002.fm.intel.com ([10.253.24.26])\n\tby orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t19 Sep 2017 02:23:19 -0700","from pg-interactive1.altera.com ([137.57.137.156])\n\tby fmsmga002.fm.intel.com with ESMTP; 19 Sep 2017 02:22:43 -0700"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-5.0 required=5.0 tests=RCVD_IN_DNSWL_HI\n\tautolearn=unavailable autolearn_force=no version=3.4.0","X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos; i=\"5.42,417,1500966000\"; d=\"scan'208\";\n\ta=\"1220781796\"","From":"chin.liang.see@intel.com","To":"u-boot@lists.denx.de,\n\tMarek Vasut ","Date":"Tue, 19 Sep 2017 17:22:20 +0800","Message-Id":"<1505812951-25088-4-git-send-email-chin.liang.see@intel.com>","X-Mailer":"git-send-email 2.2.2","In-Reply-To":"<1505812951-25088-1-git-send-email-chin.liang.see@intel.com>","References":"<1505812951-25088-1-git-send-email-chin.liang.see@intel.com>","Cc":"Tien Fong Chee ,\n\tChin Liang See ","Subject":"[U-Boot] [PATCH 03/14] arm: socfpga: stratix10: Add Clock Manager\n\tdriver for Stratix10 SoC","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"From: Chin Liang See \n\nAdd Clock Manager driver support for Stratix SoC\n\nSigned-off-by: Chin Liang See \n---\n arch/arm/mach-socfpga/Makefile | 4 +\n arch/arm/mach-socfpga/clock_manager.c | 4 +-\n arch/arm/mach-socfpga/clock_manager_s10.c | 359 +++++++++++++++++++++\n arch/arm/mach-socfpga/include/mach/clock_manager.h | 2 +\n .../mach-socfpga/include/mach/clock_manager_s10.h | 202 ++++++++++++\n arch/arm/mach-socfpga/include/mach/handoff_s10.h | 29 ++\n arch/arm/mach-socfpga/wrap_pll_config_s10.c | 46 +++\n 7 files changed, 644 insertions(+), 2 deletions(-)\n create mode 100644 arch/arm/mach-socfpga/clock_manager_s10.c\n create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_s10.h\n create mode 100644 arch/arm/mach-socfpga/include/mach/handoff_s10.h\n create mode 100644 arch/arm/mach-socfpga/wrap_pll_config_s10.c","diff":"diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile\nindex 286bfef..e5f9dd7 100644\n--- a/arch/arm/mach-socfpga/Makefile\n+++ b/arch/arm/mach-socfpga/Makefile\n@@ -30,6 +30,10 @@ obj-y\t+= pinmux_arria10.o\n obj-y\t+= reset_manager_arria10.o\n endif\n \n+ifdef CONFIG_TARGET_SOCFPGA_STRATIX10\n+obj-y\t+= clock_manager_s10.o\n+obj-y\t+= wrap_pll_config_s10.o\n+endif\n ifdef CONFIG_SPL_BUILD\n obj-y\t+= spl.o\n ifdef CONFIG_TARGET_SOCFPGA_GEN5\ndiff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c\nindex cb6ae03..f9450a4 100644\n--- a/arch/arm/mach-socfpga/clock_manager.c\n+++ b/arch/arm/mach-socfpga/clock_manager.c\n@@ -21,7 +21,7 @@ void cm_wait_for_lock(u32 mask)\n \tdo {\n #if defined(CONFIG_TARGET_SOCFPGA_GEN5)\n \t\tinter_val = readl(&clock_manager_base->inter) & mask;\n-#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)\n+#else\n \t\tinter_val = readl(&clock_manager_base->stat) & mask;\n #endif\n \t\t/* Wait for stable lock */\n@@ -52,7 +52,7 @@ int set_cpu_clk_info(void)\n \n #if defined(CONFIG_TARGET_SOCFPGA_GEN5)\n \tgd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000;\n-#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)\n+#else\n \tgd->bd->bi_ddr_freq = 0;\n #endif\n \ndiff --git a/arch/arm/mach-socfpga/clock_manager_s10.c b/arch/arm/mach-socfpga/clock_manager_s10.c\nnew file mode 100644\nindex 0000000..a9f9b07\n--- /dev/null\n+++ b/arch/arm/mach-socfpga/clock_manager_s10.c\n@@ -0,0 +1,359 @@\n+/*\n+ * Copyright (C) 2016-2017 Intel Corporation \n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0\n+ */\n+\n+#include \n+#include \n+#include \n+#include \n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+static const struct socfpga_clock_manager *clock_manager_base =\n+\t(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;\n+\n+/*\n+ * function to write the bypass register which requires a poll of the\n+ * busy bit\n+ */\n+static void cm_write_bypass_mainpll(uint32_t val)\n+{\n+\twritel(val, &clock_manager_base->main_pll.bypass);\n+\tcm_wait_for_fsm();\n+}\n+static void cm_write_bypass_perpll(uint32_t val)\n+{\n+\twritel(val, &clock_manager_base->per_pll.bypass);\n+\tcm_wait_for_fsm();\n+}\n+\n+/* function to write the ctrl register which requires a poll of the busy bit */\n+static void cm_write_ctrl(uint32_t val)\n+{\n+\twritel(val, &clock_manager_base->ctrl);\n+\tcm_wait_for_fsm();\n+}\n+\n+/*\n+ * Setup clocks while making no assumptions about previous state of the clocks.\n+ *\n+ */\n+void cm_basic_init(const struct cm_config * const cfg)\n+{\n+\tuint32_t mdiv, refclkdiv, mscnt, hscnt, vcocalib;\n+\n+\tif (cfg == 0)\n+\t\treturn;\n+\n+\t/* Put all plls in bypass */\n+\tcm_write_bypass_mainpll(CLKMGR_BYPASS_MAINPLL_ALL);\n+\tcm_write_bypass_perpll(CLKMGR_BYPASS_PERPLL_ALL);\n+\n+\t/* setup main PLL dividers */\n+\t/* calculate the vcocalib value */\n+\tmdiv = (cfg->main_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) &\n+\t\tCLKMGR_FDBCK_MDIV_MASK;\n+\trefclkdiv = (cfg->main_pll_pllglob >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &\n+\t\t CLKMGR_PLLGLOB_REFCLKDIV_MASK;\n+\tmscnt = 200 / (6 + mdiv) / refclkdiv;\n+\thscnt = (mdiv + 6) * mscnt / refclkdiv - 9;\n+\tvcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) |\n+\t\t ((mscnt & CLKMGR_VCOCALIB_MSCNT_MASK) <<\n+\t\t CLKMGR_VCOCALIB_MSCNT_OFFSET);\n+\n+\twritel((cfg->main_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK &\n+\t\t~CLKMGR_PLLGLOB_RST_MASK),\n+\t\t&clock_manager_base->main_pll.pllglob);\n+\twritel(cfg->main_pll_fdbck, &clock_manager_base->main_pll.fdbck);\n+\twritel(vcocalib, &clock_manager_base->main_pll.vcocalib);\n+\twritel(cfg->main_pll_pllc0, &clock_manager_base->main_pll.pllc0);\n+\twritel(cfg->main_pll_pllc1, &clock_manager_base->main_pll.pllc1);\n+\twritel(cfg->main_pll_nocdiv, &clock_manager_base->main_pll.nocdiv);\n+\n+\t/* setup peripheral PLL dividers */\n+\t/* calculate the vcocalib value */\n+\tmdiv = (cfg->per_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) &\n+\t\tCLKMGR_FDBCK_MDIV_MASK;\n+\trefclkdiv = (cfg->per_pll_pllglob >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &\n+\t\t CLKMGR_PLLGLOB_REFCLKDIV_MASK;\n+\tmscnt = 200 / (6 + mdiv) / refclkdiv;\n+\thscnt = (mdiv + 6) * mscnt / refclkdiv - 9;\n+\tvcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) |\n+\t\t ((mscnt & CLKMGR_VCOCALIB_MSCNT_MASK) <<\n+\t\t CLKMGR_VCOCALIB_MSCNT_OFFSET);\n+\n+\twritel((cfg->per_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK &\n+\t\t~CLKMGR_PLLGLOB_RST_MASK),\n+\t\t&clock_manager_base->per_pll.pllglob);\n+\twritel(cfg->per_pll_fdbck, &clock_manager_base->per_pll.fdbck);\n+\twritel(vcocalib, &clock_manager_base->per_pll.vcocalib);\n+\twritel(cfg->per_pll_pllc0, &clock_manager_base->per_pll.pllc0);\n+\twritel(cfg->per_pll_pllc1, &clock_manager_base->per_pll.pllc1);\n+\twritel(cfg->per_pll_emacctl, &clock_manager_base->per_pll.emacctl);\n+\twritel(cfg->per_pll_gpiodiv, &clock_manager_base->per_pll.gpiodiv);\n+\n+\t/* Take both PLL out of reset and power up */\n+\tsetbits_le32(&clock_manager_base->main_pll.pllglob,\n+\t\t CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);\n+\tsetbits_le32(&clock_manager_base->per_pll.pllglob,\n+\t\t CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);\n+\n+#define LOCKED_MASK \\\n+\t(CLKMGR_STAT_MAINPLL_LOCKED | \\\n+\tCLKMGR_STAT_PERPLL_LOCKED)\n+\n+\tcm_wait_for_lock(LOCKED_MASK);\n+\n+\t/*\n+\t * Dividers for C2 to C9 only init after PLLs are lock. We will a large\n+\t * dividers value then final value as requested by hardware behaviour\n+\t */\n+\twritel(0xff, &clock_manager_base->main_pll.mpuclk);\n+\twritel(0xff, &clock_manager_base->main_pll.nocclk);\n+\twritel(0xff, &clock_manager_base->main_pll.cntr2clk);\n+\twritel(0xff, &clock_manager_base->main_pll.cntr3clk);\n+\twritel(0xff, &clock_manager_base->main_pll.cntr4clk);\n+\twritel(0xff, &clock_manager_base->main_pll.cntr5clk);\n+\twritel(0xff, &clock_manager_base->main_pll.cntr6clk);\n+\twritel(0xff, &clock_manager_base->main_pll.cntr7clk);\n+\twritel(0xff, &clock_manager_base->main_pll.cntr8clk);\n+\twritel(0xff, &clock_manager_base->main_pll.cntr9clk);\n+\twritel(0xff, &clock_manager_base->per_pll.cntr2clk);\n+\twritel(0xff, &clock_manager_base->per_pll.cntr3clk);\n+\twritel(0xff, &clock_manager_base->per_pll.cntr4clk);\n+\twritel(0xff, &clock_manager_base->per_pll.cntr5clk);\n+\twritel(0xff, &clock_manager_base->per_pll.cntr6clk);\n+\twritel(0xff, &clock_manager_base->per_pll.cntr7clk);\n+\twritel(0xff, &clock_manager_base->per_pll.cntr8clk);\n+\twritel(0xff, &clock_manager_base->per_pll.cntr9clk);\n+\n+\twritel(cfg->main_pll_mpuclk, &clock_manager_base->main_pll.mpuclk);\n+\twritel(cfg->main_pll_nocclk, &clock_manager_base->main_pll.nocclk);\n+\twritel(cfg->main_pll_cntr2clk, &clock_manager_base->main_pll.cntr2clk);\n+\twritel(cfg->main_pll_cntr3clk, &clock_manager_base->main_pll.cntr3clk);\n+\twritel(cfg->main_pll_cntr4clk, &clock_manager_base->main_pll.cntr4clk);\n+\twritel(cfg->main_pll_cntr5clk, &clock_manager_base->main_pll.cntr5clk);\n+\twritel(cfg->main_pll_cntr6clk, &clock_manager_base->main_pll.cntr6clk);\n+\twritel(cfg->main_pll_cntr7clk, &clock_manager_base->main_pll.cntr7clk);\n+\twritel(cfg->main_pll_cntr8clk, &clock_manager_base->main_pll.cntr8clk);\n+\twritel(cfg->main_pll_cntr9clk, &clock_manager_base->main_pll.cntr9clk);\n+\twritel(cfg->per_pll_cntr2clk, &clock_manager_base->per_pll.cntr2clk);\n+\twritel(cfg->per_pll_cntr3clk, &clock_manager_base->per_pll.cntr3clk);\n+\twritel(cfg->per_pll_cntr4clk, &clock_manager_base->per_pll.cntr4clk);\n+\twritel(cfg->per_pll_cntr5clk, &clock_manager_base->per_pll.cntr5clk);\n+\twritel(cfg->per_pll_cntr6clk, &clock_manager_base->per_pll.cntr6clk);\n+\twritel(cfg->per_pll_cntr7clk, &clock_manager_base->per_pll.cntr7clk);\n+\twritel(cfg->per_pll_cntr8clk, &clock_manager_base->per_pll.cntr8clk);\n+\twritel(cfg->per_pll_cntr9clk, &clock_manager_base->per_pll.cntr9clk);\n+\n+\t/* Take all PLLs out of bypass */\n+\tcm_write_bypass_mainpll(0);\n+\tcm_write_bypass_perpll(0);\n+\n+\t/* clear safe mode / out of boot mode */\n+\tcm_write_ctrl(readl(&clock_manager_base->ctrl)\n+\t\t\t& ~(CLKMGR_CTRL_SAFEMODE));\n+\n+\t/* Now ungate non-hw-managed clocks */\n+\twritel(~0, &clock_manager_base->main_pll.en);\n+\twritel(~0, &clock_manager_base->per_pll.en);\n+\n+\t/* Clear the loss of lock bits (write 1 to clear) */\n+\twritel(CLKMGR_INTER_PERPLLLOST_MASK | CLKMGR_INTER_MAINPLLLOST_MASK,\n+\t &clock_manager_base->intrclr);\n+}\n+\n+static unsigned long cm_get_main_vco_clk_hz(void)\n+{\n+\t unsigned long fref, refdiv, mdiv, reg, vco;\n+\n+\treg = readl(&clock_manager_base->main_pll.pllglob);\n+\n+\t/* get the fref */\n+\tfref = (reg >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET) &\n+\t\tCLKMGR_PLLGLOB_VCO_PSRC_MASK;\n+\tswitch (fref) {\n+\tcase CLKMGR_VCO_PSRC_EOSC1:\n+\t\tfref = cm_get_osc_clk_hz(0);\n+\t\tbreak;\n+\tcase CLKMGR_VCO_PSRC_INTOSC:\n+\t\tfref = cm_get_intosc_clk_hz();\n+\t\tbreak;\n+\tcase CLKMGR_VCO_PSRC_F2S:\n+\t\tfref = cm_get_fpga_clk_hz();\n+\t\tbreak;\n+\t}\n+\n+\t/* get the refdiv */\n+\trefdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &\n+\t\t CLKMGR_PLLGLOB_REFCLKDIV_MASK;\n+\n+\t/* get the mdiv */\n+\treg = readl(&clock_manager_base->main_pll.fdbck);\n+\tmdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) & CLKMGR_FDBCK_MDIV_MASK;\n+\n+\tvco = fref / refdiv;\n+\tvco = vco * (6 + mdiv);\n+\treturn vco;\n+}\n+\n+static unsigned long cm_get_per_vco_clk_hz(void)\n+{\n+\tunsigned long fref, refdiv, mdiv, reg, vco;\n+\n+\treg = readl(&clock_manager_base->per_pll.pllglob);\n+\n+\t/* get the fref */\n+\tfref = (reg >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET) &\n+\t\tCLKMGR_PLLGLOB_VCO_PSRC_MASK;\n+\tswitch (fref) {\n+\tcase CLKMGR_VCO_PSRC_EOSC1:\n+\t\tfref = cm_get_osc_clk_hz(0);\n+\t\tbreak;\n+\tcase CLKMGR_VCO_PSRC_INTOSC:\n+\t\tfref = cm_get_intosc_clk_hz();\n+\t\tbreak;\n+\tcase CLKMGR_VCO_PSRC_F2S:\n+\t\tfref = cm_get_fpga_clk_hz();\n+\t\tbreak;\n+\t}\n+\n+\t/* get the refdiv */\n+\trefdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &\n+\t\t CLKMGR_PLLGLOB_REFCLKDIV_MASK;\n+\n+\t/* get the mdiv */\n+\treg = readl(&clock_manager_base->per_pll.fdbck);\n+\tmdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) & CLKMGR_FDBCK_MDIV_MASK;\n+\n+\tvco = fref / refdiv;\n+\tvco = vco * (6 + mdiv);\n+\treturn vco;\n+}\n+\n+unsigned long cm_get_mpu_clk_hz(void)\n+{\n+\tunsigned long clock = readl(&clock_manager_base->main_pll.mpuclk);\n+\tclock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;\n+\n+\tswitch (clock) {\n+\tcase CLKMGR_CLKSRC_MAIN:\n+\t\tclock = cm_get_main_vco_clk_hz();\n+\t\tclock /= (readl(&clock_manager_base->main_pll.pllc0) &\n+\t\t\t CLKMGR_PLLC0_DIV_MASK);\n+\t\tbreak;\n+\n+\tcase CLKMGR_CLKSRC_PER:\n+\t\tclock = cm_get_per_vco_clk_hz();\n+\t\tclock /= (readl(&clock_manager_base->per_pll.pllc0) &\n+\t\t\t CLKMGR_CLKCNT_MSK);\n+\t\tbreak;\n+\n+\tcase CLKMGR_CLKSRC_OSC1:\n+\t\tclock = cm_get_osc_clk_hz(0);\n+\t\tbreak;\n+\n+\tcase CLKMGR_CLKSRC_INTOSC:\n+\t\tclock = cm_get_intosc_clk_hz();\n+\t\tbreak;\n+\n+\tcase CLKMGR_CLKSRC_FPGA:\n+\t\tclock = cm_get_fpga_clk_hz();\n+\t\tbreak;\n+\t}\n+\n+\tclock /= 1 + (readl(&clock_manager_base->main_pll.mpuclk) &\n+\t\tCLKMGR_CLKCNT_MSK);\n+\treturn clock;\n+}\n+\n+unsigned int cm_get_l3_main_clk_hz(void)\n+{\n+\tuint32_t clock = readl(&clock_manager_base->main_pll.nocclk);\n+\tclock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;\n+\n+\tswitch (clock) {\n+\tcase CLKMGR_CLKSRC_MAIN:\n+\t\tclock = cm_get_main_vco_clk_hz();\n+\t\tclock /= (readl(&clock_manager_base->main_pll.pllc1) &\n+\t\t\t CLKMGR_PLLC0_DIV_MASK);\n+\t\tbreak;\n+\n+\tcase CLKMGR_CLKSRC_PER:\n+\t\tclock = cm_get_per_vco_clk_hz();\n+\t\tclock /= (readl(&clock_manager_base->per_pll.pllc1) &\n+\t\t\t CLKMGR_CLKCNT_MSK);\n+\t\tbreak;\n+\n+\tcase CLKMGR_CLKSRC_OSC1:\n+\t\tclock = cm_get_osc_clk_hz(0);\n+\t\tbreak;\n+\n+\tcase CLKMGR_CLKSRC_INTOSC:\n+\t\tclock = cm_get_intosc_clk_hz();\n+\t\tbreak;\n+\n+\tcase CLKMGR_CLKSRC_FPGA:\n+\t\tclock = cm_get_fpga_clk_hz();\n+\t\tbreak;\n+\t}\n+\n+\tclock /= 1 + (readl(&clock_manager_base->main_pll.nocclk) &\n+\t\tCLKMGR_CLKCNT_MSK);\n+\treturn clock;\n+}\n+\n+unsigned int cm_get_mmc_controller_clk_hz(void)\n+{\n+\tuint32_t clock = readl(&clock_manager_base->per_pll.cntr6clk);\n+\tclock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;\n+\n+\tswitch (clock) {\n+\tcase CLKMGR_CLKSRC_MAIN:\n+\t\tclock = cm_get_l3_main_clk_hz();\n+\t\tclock /= 1 + (readl(&clock_manager_base->main_pll.cntr6clk) &\n+\t\t\tCLKMGR_CLKCNT_MSK);\n+\t\tbreak;\n+\n+\tcase CLKMGR_CLKSRC_PER:\n+\t\tclock = cm_get_l3_main_clk_hz();\n+\t\tclock /= 1 + (readl(&clock_manager_base->per_pll.cntr6clk) &\n+\t\t\tCLKMGR_CLKCNT_MSK);\n+\t\tbreak;\n+\n+\tcase CLKMGR_CLKSRC_OSC1:\n+\t\tclock = cm_get_osc_clk_hz(0);\n+\t\tbreak;\n+\n+\tcase CLKMGR_CLKSRC_INTOSC:\n+\t\tclock = cm_get_intosc_clk_hz();\n+\t\tbreak;\n+\n+\tcase CLKMGR_CLKSRC_FPGA:\n+\t\tclock = cm_get_fpga_clk_hz();\n+\t\tbreak;\n+\t}\n+\treturn clock/4;\n+}\n+\n+unsigned int cm_get_l4_sp_clk_hz(void)\n+{\n+\tuint32_t clock = cm_get_l3_main_clk_hz();\n+\n+\tclock /= (1 << ((readl(&clock_manager_base->main_pll.nocdiv) >>\n+\t\t CLKMGR_NOCDIV_L4SPCLK_OFFSET) & CLKMGR_CLKCNT_MSK));\n+\treturn clock;\n+}\n+\n+void cm_print_clock_quick_summary(void)\n+{\n+\tprintf(\"MPU %d kHz\\n\", (u32)(cm_get_mpu_clk_hz() / 1000));\n+\tprintf(\"L3 main %d kHz\\n\", cm_get_l3_main_clk_hz() / 1000);\n+\tprintf(\"Main VCO %d kHz\\n\", (u32)(cm_get_main_vco_clk_hz() / 1000));\n+\tprintf(\"Per VCO %d kHz\\n\", (u32)(cm_get_per_vco_clk_hz() / 1000));\n+\tprintf(\"EOSC1 %d kHz\\n\", cm_get_osc_clk_hz(0) / 1000);\n+\tprintf(\"HPS MMC %d kHz\\n\", cm_get_mmc_controller_clk_hz() / 1000);\n+\tprintf(\"UART %d kHz\\n\", cm_get_l4_sp_clk_hz() / 1000);\n+}\ndiff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h\nindex 4c6b1f8..ddf814f 100644\n--- a/arch/arm/mach-socfpga/include/mach/clock_manager.h\n+++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h\n@@ -17,6 +17,8 @@ void cm_print_clock_quick_summary(void);\n #include \n #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)\n #include \n+#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)\n+#include \n #endif\n \n #endif /* _CLOCK_MANAGER_H_ */\ndiff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h\nnew file mode 100644\nindex 0000000..c99ad97\n--- /dev/null\n+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h\n@@ -0,0 +1,202 @@\n+/*\n+ * Copyright (C) 2016-2017 Intel Corporation \n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0\n+ */\n+\n+#ifndef\t_CLOCK_MANAGER_S10_\n+#define\t_CLOCK_MANAGER_S10_\n+\n+/* Clock speed accessors */\n+unsigned long cm_get_mpu_clk_hz(void);\n+unsigned long cm_get_sdram_clk_hz(void);\n+unsigned int cm_get_l4_sp_clk_hz(void);\n+unsigned int cm_get_mmc_controller_clk_hz(void);\n+unsigned int cm_get_qspi_controller_clk_hz(void);\n+unsigned int cm_get_spi_controller_clk_hz(void);\n+const unsigned int cm_get_osc_clk_hz(const int osc);\n+const unsigned int cm_get_f2s_per_ref_clk_hz(void);\n+const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);\n+const unsigned int cm_get_intosc_clk_hz(void);\n+const unsigned int cm_get_fpga_clk_hz(void);\n+\n+/* Clock configuration accessors */\n+const struct cm_config * const cm_get_default_config(void);\n+\n+struct cm_config {\n+\t/* main group */\n+\tuint32_t main_pll_mpuclk;\n+\tuint32_t main_pll_nocclk;\n+\tuint32_t main_pll_cntr2clk;\n+\tuint32_t main_pll_cntr3clk;\n+\tuint32_t main_pll_cntr4clk;\n+\tuint32_t main_pll_cntr5clk;\n+\tuint32_t main_pll_cntr6clk;\n+\tuint32_t main_pll_cntr7clk;\n+\tuint32_t main_pll_cntr8clk;\n+\tuint32_t main_pll_cntr9clk;\n+\tuint32_t main_pll_nocdiv;\n+\tuint32_t main_pll_pllglob;\n+\tuint32_t main_pll_fdbck;\n+\tuint32_t main_pll_pllc0;\n+\tuint32_t main_pll_pllc1;\n+\tuint32_t spare;\n+\n+\t/* peripheral group */\n+\tuint32_t per_pll_cntr2clk;\n+\tuint32_t per_pll_cntr3clk;\n+\tuint32_t per_pll_cntr4clk;\n+\tuint32_t per_pll_cntr5clk;\n+\tuint32_t per_pll_cntr6clk;\n+\tuint32_t per_pll_cntr7clk;\n+\tuint32_t per_pll_cntr8clk;\n+\tuint32_t per_pll_cntr9clk;\n+\tuint32_t per_pll_emacctl;\n+\tuint32_t per_pll_gpiodiv;\n+\tuint32_t per_pll_pllglob;\n+\tuint32_t per_pll_fdbck;\n+\tuint32_t per_pll_pllc0;\n+\tuint32_t per_pll_pllc1;\n+\n+\t/* incoming clock */\n+\tuint32_t hps_osc_clk_hz;\n+\tuint32_t fpga_clk_hz;\n+};\n+\n+void cm_basic_init(const struct cm_config * const cfg);\n+\n+struct socfpga_clock_manager_main_pll {\n+\tu32\ten;\n+\tu32\tens;\n+\tu32\tenr;\n+\tu32\tbypass;\n+\tu32\tbypasss;\n+\tu32\tbypassr;\n+\tu32\tmpuclk;\n+\tu32\tnocclk;\n+\tu32\tcntr2clk;\n+\tu32\tcntr3clk;\n+\tu32\tcntr4clk;\n+\tu32\tcntr5clk;\n+\tu32\tcntr6clk;\n+\tu32\tcntr7clk;\n+\tu32\tcntr8clk;\n+\tu32\tcntr9clk;\n+\tu32\tnocdiv;\n+\tu32\tpllglob;\n+\tu32\tfdbck;\n+\tu32\tmem;\n+\tu32\tmemstat;\n+\tu32\tpllc0;\n+\tu32\tpllc1;\n+\tu32\tvcocalib;\n+\tu32\t_pad_0x90_0xA0[5];\n+};\n+\n+struct socfpga_clock_manager_per_pll {\n+\tu32\ten;\n+\tu32\tens;\n+\tu32\tenr;\n+\tu32\tbypass;\n+\tu32\tbypasss;\n+\tu32\tbypassr;\n+\tu32\tcntr2clk;\n+\tu32\tcntr3clk;\n+\tu32\tcntr4clk;\n+\tu32\tcntr5clk;\n+\tu32\tcntr6clk;\n+\tu32\tcntr7clk;\n+\tu32\tcntr8clk;\n+\tu32\tcntr9clk;\n+\tu32\temacctl;\n+\tu32\tgpiodiv;\n+\tu32\tpllglob;\n+\tu32\tfdbck;\n+\tu32\tmem;\n+\tu32\tmemstat;\n+\tu32\tpllc0;\n+\tu32\tpllc1;\n+\tu32\tvcocalib;\n+\tu32\t_pad_0x100_0x124[10];\n+};\n+\n+struct socfpga_clock_manager {\n+\tu32\tctrl;\n+\tu32\tstat;\n+\tu32\ttestioctrl;\n+\tu32\tintrgen;\n+\tu32\tintrmsk;\n+\tu32\tintrclr;\n+\tu32\tintrsts;\n+\tu32\tintrstk;\n+\tu32\tintrraw;\n+\tu32\t_pad_0x24_0x2c[3];\n+\tstruct socfpga_clock_manager_main_pll main_pll;\n+\tstruct socfpga_clock_manager_per_pll per_pll;\n+};\n+\n+#define CLKMGR_CTRL_SAFEMODE\t\t\t\t(1 << 0)\n+#define CLKMGR_BYPASS_MAINPLL_ALL\t\t\t0x00000007\n+#define CLKMGR_BYPASS_PERPLL_ALL\t\t\t0x0000007f\n+\n+#define CLKMGR_INTER_MAINPLLLOCKED_MASK\t\t\t0x00000001\n+#define CLKMGR_INTER_PERPLLLOCKED_MASK\t\t\t0x00000002\n+#define CLKMGR_INTER_MAINPLLLOST_MASK\t\t\t0x00000004\n+#define CLKMGR_INTER_PERPLLLOST_MASK\t\t\t0x00000008\n+#define CLKMGR_STAT_BUSY\t\t\t\t(1 << 0)\n+#define CLKMGR_STAT_MAINPLL_LOCKED\t\t\t(1 << 8)\n+#define CLKMGR_STAT_PERPLL_LOCKED\t\t\t(1 << 9)\n+\n+#define CLKMGR_PLLGLOB_PD_MASK\t\t\t\t0x00000001\n+#define CLKMGR_PLLGLOB_RST_MASK\t\t\t\t0x00000002\n+#define CLKMGR_PLLGLOB_VCO_PSRC_MASK\t\t\t0X3\n+#define CLKMGR_PLLGLOB_VCO_PSRC_OFFSET\t\t\t16\n+#define CLKMGR_VCO_PSRC_EOSC1\t\t\t\t0\n+#define CLKMGR_VCO_PSRC_INTOSC\t\t\t\t1\n+#define CLKMGR_VCO_PSRC_F2S\t\t\t\t2\n+#define CLKMGR_PLLGLOB_REFCLKDIV_MASK\t\t\t0X3f\n+#define CLKMGR_PLLGLOB_REFCLKDIV_OFFSET\t\t\t8\n+\n+#define CLKMGR_CLKSRC_MASK\t\t\t\t0x7\n+#define CLKMGR_CLKSRC_OFFSET\t\t\t\t16\n+#define CLKMGR_CLKSRC_MAIN\t\t\t\t0\n+#define CLKMGR_CLKSRC_PER\t\t\t\t1\n+#define CLKMGR_CLKSRC_OSC1\t\t\t\t2\n+#define CLKMGR_CLKSRC_INTOSC\t\t\t\t3\n+#define CLKMGR_CLKSRC_FPGA\t\t\t\t4\n+#define CLKMGR_CLKCNT_MSK\t\t\t\t0x7ff\n+\n+#define CLKMGR_FDBCK_MDIV_MASK\t\t\t\t0xff\n+#define CLKMGR_FDBCK_MDIV_OFFSET\t\t\t24\n+\n+#define CLKMGR_PLLC0_DIV_MASK\t\t\t\t0xff\n+#define CLKMGR_PLLC1_DIV_MASK\t\t\t\t0xff\n+#define CLKMGR_PLLC0_EN_OFFSET\t\t\t\t27\n+#define CLKMGR_PLLC1_EN_OFFSET\t\t\t\t24\n+\n+#define CLKMGR_NOCDIV_L4MAIN_OFFSET\t\t\t0\n+#define CLKMGR_NOCDIV_L4MPCLK_OFFSET\t\t\t8\n+#define CLKMGR_NOCDIV_L4SPCLK_OFFSET\t\t\t16\n+#define CLKMGR_NOCDIV_CSATCLK_OFFSET\t\t\t24\n+#define CLKMGR_NOCDIV_CSTRACECLK_OFFSET\t\t\t26\n+#define CLKMGR_NOCDIV_CSPDBGCLK_OFFSET\t\t\t28\n+\n+#define CLKMGR_NOCDIV_L4SPCLK_MASK\t\t\t0X3\n+#define CLKMGR_NOCDIV_DIV1\t\t\t\t0\n+#define CLKMGR_NOCDIV_DIV2\t\t\t\t1\n+#define CLKMGR_NOCDIV_DIV4\t\t\t\t2\n+#define CLKMGR_NOCDIV_DIV8\t\t\t\t3\n+#define CLKMGR_CSPDBGCLK_DIV1\t\t\t\t0\n+#define CLKMGR_CSPDBGCLK_DIV4\t\t\t\t1\n+\n+#define CLKMGR_VCOCALIB_MSCNT_MASK\t\t\t0xff\n+#define CLKMGR_VCOCALIB_MSCNT_OFFSET\t\t\t9\n+#define CLKMGR_VCOCALIB_HSCNT_MASK\t\t\t0xff\n+\n+#define CLKMGR_EMACCTL_EMAC0SEL_OFFSET\t\t\t26\n+#define CLKMGR_EMACCTL_EMAC1SEL_OFFSET\t\t\t27\n+#define CLKMGR_EMACCTL_EMAC2SEL_OFFSET\t\t\t28\n+\n+#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK\t\t0x00000020\n+\n+#endif /* _CLOCK_MANAGER_S10_ */\ndiff --git a/arch/arm/mach-socfpga/include/mach/handoff_s10.h b/arch/arm/mach-socfpga/include/mach/handoff_s10.h\nnew file mode 100644\nindex 0000000..d4b89ac\n--- /dev/null\n+++ b/arch/arm/mach-socfpga/include/mach/handoff_s10.h\n@@ -0,0 +1,29 @@\n+/*\n+ * Copyright (C) 2017 Intel Corporation \n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0\n+ */\n+\n+#ifndef _HANDOFF_S10_H_\n+#define _HANDOFF_S10_H_\n+\n+/*\n+ * Offset for HW handoff from Quartus tools\n+ */\n+#define CONFIG_HANDOFF_BASE\t\t0xFFE3F000\n+#define CONFIG_HANDOFF_MUX\t\t(CONFIG_HANDOFF_BASE + 0x10)\n+#define CONFIG_HANDOFF_IOCTL\t\t(CONFIG_HANDOFF_BASE + 0x1A0)\n+#define CONFIG_HANDOFF_FPGA\t\t(CONFIG_HANDOFF_BASE + 0x330)\n+#define CONFIG_HANODFF_DELAY\t\t(CONFIG_HANDOFF_BASE + 0x3F0)\n+#define CONFIG_HANDOFF_CLOCK\t\t(CONFIG_HANDOFF_BASE + 0x580)\n+#define CONFIG_HANDOFF_MISC\t\t(CONFIG_HANDOFF_BASE + 0x610)\n+#define CONFIG_HANDOFF_MAGIC_MUX\t0x504D5558\n+#define CONFIG_HANDOFF_MAGIC_IOCTL\t0x494F4354\n+#define CONFIG_HANDOFF_MAGIC_FPGA\t0x46504741\n+#define CONFIG_HANDOFF_MAGIC_DELAY\t0x444C4159\n+#define CONFIG_HANDOFF_MAGIC_CLOCK\t0x434C4B53\n+#define CONFIG_HANDOFF_MAGIC_MISC\t0x4D495343\n+#define CONFIG_HANDOFF_OFFSET_LENGTH\t0x4\n+#define CONFIG_HANDOFF_OFFSET_DATA\t0x10\n+\n+#endif /* _HANDOFF_S10_H_ */\ndiff --git a/arch/arm/mach-socfpga/wrap_pll_config_s10.c b/arch/arm/mach-socfpga/wrap_pll_config_s10.c\nnew file mode 100644\nindex 0000000..2a624d5\n--- /dev/null\n+++ b/arch/arm/mach-socfpga/wrap_pll_config_s10.c\n@@ -0,0 +1,46 @@\n+/*\n+ * Copyright (C) 2016-2017 Intel Corporation \n+ *\n+ * SPDX-License-Identifier: GPL-2.0\n+ */\n+\n+#include \n+#include \n+#include \n+#include \n+\n+const struct cm_config * const cm_get_default_config(void)\n+{\n+\tstruct cm_config *cm_handoff_cfg = (struct cm_config *)\n+\t\t(CONFIG_HANDOFF_CLOCK + CONFIG_HANDOFF_OFFSET_DATA);\n+\tu32 *conversion = (u32 *)cm_handoff_cfg;\n+\tu32 i;\n+\n+\tif (swab32(readl(CONFIG_HANDOFF_CLOCK)) == CONFIG_HANDOFF_MAGIC_CLOCK) {\n+\t\twritel(swab32(readl(CONFIG_HANDOFF_CLOCK)),\n+\t\t\tCONFIG_HANDOFF_CLOCK);\n+\t\tfor (i = 0; i < (sizeof(*cm_handoff_cfg) / sizeof(u32)); i++)\n+\t\t\tconversion[i] = swab32(conversion[i]);\n+\t\treturn cm_handoff_cfg;\n+\t} else if (readl(CONFIG_HANDOFF_CLOCK) == CONFIG_HANDOFF_MAGIC_CLOCK) {\n+\t\treturn cm_handoff_cfg;\n+\t} else\n+\t\treturn 0;\n+}\n+\n+const unsigned int cm_get_osc_clk_hz(const int osc)\n+{\n+\treturn 25000000;\n+}\n+\n+const unsigned int cm_get_intosc_clk_hz(void)\n+{\n+\t/* theory maximum internal osc clock */\n+\treturn 460000000;\n+}\n+\n+const unsigned int cm_get_fpga_clk_hz(void)\n+{\n+\t/* assuming 50MHz */\n+\treturn 50000000;\n+}\n","prefixes":["U-Boot","03/14"]}