{"id":815361,"url":"http://patchwork.ozlabs.org/api/patches/815361/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1505812951-25088-5-git-send-email-chin.liang.see@intel.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1505812951-25088-5-git-send-email-chin.liang.see@intel.com>","list_archive_url":null,"date":"2017-09-19T09:22:21","name":"[U-Boot,04/14] arm: socfpga: stratix10: Add Reset Manager driver for Stratix10 SoC","commit_ref":null,"pull_url":null,"state":"superseded","archived":false,"hash":"f6d905b7f4a3eb40882d7b0da11d0c9bcd2adf48","submitter":{"id":70182,"url":"http://patchwork.ozlabs.org/api/people/70182/?format=json","name":"See, Chin Liang","email":"chin.liang.see@intel.com"},"delegate":{"id":1699,"url":"http://patchwork.ozlabs.org/api/users/1699/?format=json","username":"marex","first_name":"Marek","last_name":"Vasut","email":"marek.vasut@gmail.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1505812951-25088-5-git-send-email-chin.liang.see@intel.com/mbox/","series":[{"id":3810,"url":"http://patchwork.ozlabs.org/api/series/3810/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=3810","date":"2017-09-19T09:22:17","name":"Enable Stratix10 SoC support","version":1,"mbox":"http://patchwork.ozlabs.org/series/3810/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/815361/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/815361/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xxHZ002Rxz9ryr\n\tfor ;\n\tTue, 19 Sep 2017 19:26:31 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 9EA4DC21D70; Tue, 19 Sep 2017 09:24:21 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 3A177C21E68;\n\tTue, 19 Sep 2017 09:23:31 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 59529C21E61; Tue, 19 Sep 2017 09:23:26 +0000 (UTC)","from mga03.intel.com (mga03.intel.com [134.134.136.65])\n\tby lists.denx.de (Postfix) with ESMTPS id A3869C21EC1\n\tfor ; Tue, 19 Sep 2017 09:23:21 +0000 (UTC)","from fmsmga002.fm.intel.com ([10.253.24.26])\n\tby orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t19 Sep 2017 02:23:21 -0700","from pg-interactive1.altera.com ([137.57.137.156])\n\tby fmsmga002.fm.intel.com with ESMTP; 19 Sep 2017 02:22:45 -0700"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-5.0 required=5.0 tests=RCVD_IN_DNSWL_HI\n\tautolearn=unavailable autolearn_force=no version=3.4.0","X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos; i=\"5.42,417,1500966000\"; d=\"scan'208\";\n\ta=\"1220781856\"","From":"chin.liang.see@intel.com","To":"u-boot@lists.denx.de,\n\tMarek Vasut ","Date":"Tue, 19 Sep 2017 17:22:21 +0800","Message-Id":"<1505812951-25088-5-git-send-email-chin.liang.see@intel.com>","X-Mailer":"git-send-email 2.2.2","In-Reply-To":"<1505812951-25088-1-git-send-email-chin.liang.see@intel.com>","References":"<1505812951-25088-1-git-send-email-chin.liang.see@intel.com>","Cc":"Tien Fong Chee ,\n\tChin Liang See ","Subject":"[U-Boot] [PATCH 04/14] arm: socfpga: stratix10: Add Reset Manager\n\tdriver for Stratix10 SoC","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"From: Chin Liang See \n\nAdd Reset Manager driver support for Stratix SoC\n\nSigned-off-by: Chin Liang See \n---\n arch/arm/mach-socfpga/Makefile | 1 +\n arch/arm/mach-socfpga/include/mach/reset_manager.h | 2 +\n .../mach-socfpga/include/mach/reset_manager_s10.h | 116 +++++++++++++++++\n arch/arm/mach-socfpga/reset_manager.c | 5 +\n arch/arm/mach-socfpga/reset_manager_s10.c | 140 +++++++++++++++++++++\n include/dt-bindings/reset/altr,rst-mgr-s10.h | 97 ++++++++++++++\n 6 files changed, 361 insertions(+)\n create mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_s10.h\n create mode 100644 arch/arm/mach-socfpga/reset_manager_s10.c\n create mode 100644 include/dt-bindings/reset/altr,rst-mgr-s10.h","diff":"diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile\nindex e5f9dd7..f10b05c 100644\n--- a/arch/arm/mach-socfpga/Makefile\n+++ b/arch/arm/mach-socfpga/Makefile\n@@ -32,6 +32,7 @@ endif\n \n ifdef CONFIG_TARGET_SOCFPGA_STRATIX10\n obj-y\t+= clock_manager_s10.o\n+obj-y\t+= reset_manager_s10.o\n obj-y\t+= wrap_pll_config_s10.o\n endif\n ifdef CONFIG_SPL_BUILD\ndiff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h\nindex 6591745..577fcce 100644\n--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h\n+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h\n@@ -45,6 +45,8 @@ void socfpga_per_reset_all(void);\n #include \n #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)\n #include \n+#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)\n+#include \n #endif\n \n #endif /* _RESET_MANAGER_H_ */\ndiff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h\nnew file mode 100644\nindex 0000000..07ada59\n--- /dev/null\n+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h\n@@ -0,0 +1,116 @@\n+/*\n+ * Copyright (C) 2016-2017 Intel Corporation \n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0\n+ */\n+\n+#ifndef\t_RESET_MANAGER_S10_\n+#define\t_RESET_MANAGER_S10_\n+\n+void reset_cpu(ulong addr);\n+void reset_deassert_peripherals_handoff(void);\n+\n+void socfpga_bridges_reset(int enable);\n+\n+void socfpga_per_reset(u32 reset, int set);\n+void socfpga_per_reset_all(void);\n+\n+struct socfpga_reset_manager {\n+\tu32\tstatus;\n+\tu32\tmpu_rst_stat;\n+\tu32\tmisc_stat;\n+\tu32\tpadding1;\n+\tu32\thdsk_en;\n+\tu32\thdsk_req;\n+\tu32\thdsk_ack;\n+\tu32\thdsk_stall;\n+\tu32 mpu_mod_reset;\n+\tu32 per_mod_reset; /* stated as per0_mod_reset in S10 datasheet */\n+\tu32 per2_mod_reset; /* stated as per1_mod_reset in S10 datasheet */\n+\tu32 brg_mod_reset;\n+\tu32\tpadding2;\n+\tu32 cold_mod_reset;\n+\tu32\tpadding3;\n+\tu32 dbg_mod_reset;\n+\tu32 tap_mod_reset;\n+\tu32\tpadding4;\n+\tu32\tpadding5;\n+\tu32 brg_warm_mask;\n+\tu32\tpadding6[3];\n+\tu32 tst_stat;\n+\tu32\tpadding7;\n+\tu32 hdsk_timeout;\n+\tu32 mpul2flushtimeout;\n+\tu32 dbghdsktimeout;\n+};\n+\n+#define RSTMGR_MPUMODRST_CORE0\t\t0\n+#define RSTMGR_PER0MODRST_OCP_MASK\t0x0020bf00\n+#define RSTMGR_BRGMODRST_DDRSCH_MASK\t0X00000040\n+\n+/*\n+ * Define a reset identifier, from which a permodrst bank ID\n+ * and reset ID can be extracted using the subsequent macros\n+ * RSTMGR_RESET() and RSTMGR_BANK().\n+ */\n+#define RSTMGR_BANK_OFFSET\t8\n+#define RSTMGR_BANK_MASK\t0x7\n+#define RSTMGR_RESET_OFFSET\t0\n+#define RSTMGR_RESET_MASK\t0x1f\n+#define RSTMGR_DEFINE(_bank, _offset)\t\t\\\n+\t((_bank) << RSTMGR_BANK_OFFSET) | ((_offset) << RSTMGR_RESET_OFFSET)\n+\n+/* Extract reset ID from the reset identifier. */\n+#define RSTMGR_RESET(_reset)\t\t\t\\\n+\t(((_reset) >> RSTMGR_RESET_OFFSET) & RSTMGR_RESET_MASK)\n+\n+/* Extract bank ID from the reset identifier. */\n+#define RSTMGR_BANK(_reset)\t\t\t\\\n+\t(((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK)\n+\n+/*\n+ * SocFPGA Stratix10 reset IDs, bank mapping is as follows:\n+ * 0 ... mpumodrst\n+ * 1 ... per0modrst\n+ * 2 ... per1modrst\n+ * 3 ... brgmodrst\n+ */\n+#define RSTMGR_EMAC0\t\tRSTMGR_DEFINE(1, 0)\n+#define RSTMGR_EMAC1\t\tRSTMGR_DEFINE(1, 1)\n+#define RSTMGR_EMAC2\t\tRSTMGR_DEFINE(1, 2)\n+#define RSTMGR_USB0\t\tRSTMGR_DEFINE(1, 3)\n+#define RSTMGR_USB1\t\tRSTMGR_DEFINE(1, 4)\n+#define RSTMGR_NAND\t\tRSTMGR_DEFINE(1, 5)\n+#define RSTMGR_SDMMC\t\tRSTMGR_DEFINE(1, 7)\n+#define RSTMGR_EMAC0_OCP\tRSTMGR_DEFINE(1, 8)\n+#define RSTMGR_EMAC1_OCP\tRSTMGR_DEFINE(1, 9)\n+#define RSTMGR_EMAC2_OCP\tRSTMGR_DEFINE(1, 10)\n+#define RSTMGR_USB0_OCP\t\tRSTMGR_DEFINE(1, 11)\n+#define RSTMGR_USB1_OCP\t\tRSTMGR_DEFINE(1, 12)\n+#define RSTMGR_NAND_OCP\t\tRSTMGR_DEFINE(1, 13)\n+#define RSTMGR_SDMMC_OCP\tRSTMGR_DEFINE(1, 15)\n+#define RSTMGR_DMA\t\tRSTMGR_DEFINE(1, 16)\n+#define RSTMGR_SPIM0\t\tRSTMGR_DEFINE(1, 17)\n+#define RSTMGR_SPIM1\t\tRSTMGR_DEFINE(1, 18)\n+#define RSTMGR_L4WD0\t\tRSTMGR_DEFINE(2, 0)\n+#define RSTMGR_L4WD1\t\tRSTMGR_DEFINE(2, 1)\n+#define RSTMGR_L4WD2\t\tRSTMGR_DEFINE(2, 2)\n+#define RSTMGR_L4WD3\t\tRSTMGR_DEFINE(2, 3)\n+#define RSTMGR_OSC1TIMER0\tRSTMGR_DEFINE(2, 4)\n+#define RSTMGR_I2C0\t\tRSTMGR_DEFINE(2, 8)\n+#define RSTMGR_I2C1\t\tRSTMGR_DEFINE(2, 9)\n+#define RSTMGR_I2C2\t\tRSTMGR_DEFINE(2, 10)\n+#define RSTMGR_I2C3\t\tRSTMGR_DEFINE(2, 11)\n+#define RSTMGR_I2C4\t\tRSTMGR_DEFINE(2, 12)\n+#define RSTMGR_UART0\t\tRSTMGR_DEFINE(2, 16)\n+#define RSTMGR_UART1\t\tRSTMGR_DEFINE(2, 17)\n+#define RSTMGR_GPIO0\t\tRSTMGR_DEFINE(2, 24)\n+#define RSTMGR_GPIO1\t\tRSTMGR_DEFINE(2, 25)\n+#define RSTMGR_SDR\t\tRSTMGR_DEFINE(3, 6)\n+\n+void socfpga_emac_manage_reset(const unsigned int of_reset_id, u32 state);\n+\n+/* Create a human-readable reference to SoCFPGA reset. */\n+#define SOCFPGA_RESET(_name)\tRSTMGR_##_name\n+\n+#endif /* _RESET_MANAGER_S10_ */\ndiff --git a/arch/arm/mach-socfpga/reset_manager.c b/arch/arm/mach-socfpga/reset_manager.c\nindex 29438ed..9acbf42 100644\n--- a/arch/arm/mach-socfpga/reset_manager.c\n+++ b/arch/arm/mach-socfpga/reset_manager.c\n@@ -20,8 +20,13 @@ static const struct socfpga_reset_manager *reset_manager_base =\n void reset_cpu(ulong addr)\n {\n \t/* request a warm reset */\n+#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)\n+\twritel((1 << RSTMGR_MPUMODRST_CORE0),\n+\t &reset_manager_base->mpu_mod_reset);\n+#else\n \twritel(1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB,\n \t &reset_manager_base->ctrl);\n+#endif\n \t/*\n \t * infinite loop here as watchdog will trigger and reset\n \t * the processor\ndiff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c\nnew file mode 100644\nindex 0000000..81bad11\n--- /dev/null\n+++ b/arch/arm/mach-socfpga/reset_manager_s10.c\n@@ -0,0 +1,140 @@\n+/*\n+ * Copyright (C) 2016-2017 Intel Corporation \n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0\n+ */\n+\n+#include \n+#include \n+#include \n+#include \n+#include \n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+static const struct socfpga_reset_manager *reset_manager_base =\n+\t\t(void *)SOCFPGA_RSTMGR_ADDRESS;\n+static const struct socfpga_system_manager *system_manager_base =\n+\t\t(void *)SOCFPGA_SYSMGR_ADDRESS;\n+\n+/* Assert or de-assert SoCFPGA reset manager reset. */\n+void socfpga_per_reset(u32 reset, int set)\n+{\n+\tconst void *reg;\n+\n+\tif (RSTMGR_BANK(reset) == 0)\n+\t\treg = &reset_manager_base->mpu_mod_reset;\n+\telse if (RSTMGR_BANK(reset) == 1)\n+\t\treg = &reset_manager_base->per_mod_reset;\n+\telse if (RSTMGR_BANK(reset) == 2)\n+\t\treg = &reset_manager_base->per2_mod_reset;\n+\telse if (RSTMGR_BANK(reset) == 3)\n+\t\treg = &reset_manager_base->brg_mod_reset;\n+\telse\t/* Invalid reset register, do nothing */\n+\t\treturn;\n+\n+\tif (set)\n+\t\tsetbits_le32(reg, 1 << RSTMGR_RESET(reset));\n+\telse\n+\t\tclrbits_le32(reg, 1 << RSTMGR_RESET(reset));\n+}\n+\n+/*\n+ * Assert reset on every peripheral but L4WD0.\n+ * Watchdog must be kept intact to prevent glitches\n+ * and/or hangs.\n+ */\n+void socfpga_per_reset_all(void)\n+{\n+\tconst u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));\n+\n+\t/* disable all except OCP and l4wd0. OCP disable later */\n+\twritel(~(l4wd0 | RSTMGR_PER0MODRST_OCP_MASK),\n+\t &reset_manager_base->per_mod_reset);\n+\twritel(~l4wd0, &reset_manager_base->per_mod_reset);\n+\twritel(0xffffffff, &reset_manager_base->per2_mod_reset);\n+}\n+\n+void socfpga_bridges_reset(int enable)\n+{\n+\tif (enable) {\n+\t\t/* clear idle request to all bridges */\n+\t\tsetbits_le32(&system_manager_base->noc_idlereq_clr, ~0);\n+\n+\t\t/* Release bridges from reset state per handoff value */\n+\t\tclrbits_le32(&reset_manager_base->brg_mod_reset, ~0);\n+\n+\t\t/* Poll until all idleack to 0 */\n+\t\twhile (readl(&system_manager_base->noc_idleack))\n+\t\t\t;\n+\t} else {\n+\t\t/* set idle request to all bridges */\n+\t\twritel(~0, &system_manager_base->noc_idlereq_set);\n+\n+\t\t/* Enable the NOC timeout */\n+\t\twritel(1, &system_manager_base->noc_timeout);\n+\n+\t\t/* Poll until all idleack to 1 */\n+\t\twhile ((readl(&system_manager_base->noc_idleack) ^\n+\t\t\t(SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK)))\n+\t\t\t;\n+\n+\t\t/* Poll until all idlestatus to 1 */\n+\t\twhile ((readl(&system_manager_base->noc_idlestatus) ^\n+\t\t\t(SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK)))\n+\t\t\t;\n+\n+\t\t/* Put all bridges (except NOR DDR scheduler) into reset */\n+\t\tsetbits_le32(&reset_manager_base->brg_mod_reset,\n+\t\t\t ~RSTMGR_BRGMODRST_DDRSCH_MASK);\n+\n+\t\t/* Disable NOC timeout */\n+\t\twritel(0, &system_manager_base->noc_timeout);\n+\t}\n+}\n+\n+/* of_reset_id: emac reset id\n+ * state: 0 - disable reset, !0 - enable reset\n+ */\n+void socfpga_emac_manage_reset(const unsigned int of_reset_id, u32 state)\n+{\n+\tu32 reset_emac;\n+\tu32 reset_emacocp;\n+\n+\t/* hardcode this now */\n+\tswitch (of_reset_id) {\n+\tcase EMAC0_RESET:\n+\t\treset_emac = SOCFPGA_RESET(EMAC0);\n+\t\treset_emacocp = SOCFPGA_RESET(EMAC0_OCP);\n+\t\tbreak;\n+\tcase EMAC1_RESET:\n+\t\treset_emac = SOCFPGA_RESET(EMAC1);\n+\t\treset_emacocp = SOCFPGA_RESET(EMAC1_OCP);\n+\t\tbreak;\n+\tcase EMAC2_RESET:\n+\t\treset_emac = SOCFPGA_RESET(EMAC2);\n+\t\treset_emacocp = SOCFPGA_RESET(EMAC2_OCP);\n+\t\tbreak;\n+\tdefault:\n+\t\tprintf(\"GMAC: Invalid reset ID (%i)!\\n\", of_reset_id);\n+\t\thang();\n+\t\tbreak;\n+\t}\n+\n+\t/* Reset ECC OCP first */\n+\tsocfpga_per_reset(reset_emacocp, state);\n+\n+\t/* Release the EMAC controller from reset */\n+\tsocfpga_per_reset(reset_emac, state);\n+}\n+\n+/*\n+ * Release peripherals from reset based on handoff\n+ */\n+void reset_deassert_peripherals_handoff(void)\n+{\n+\twritel(0, &reset_manager_base->per2_mod_reset);\n+\t/* Enable OCP first */\n+\twritel(~RSTMGR_PER0MODRST_OCP_MASK, &reset_manager_base->per_mod_reset);\n+\twritel(0, &reset_manager_base->per_mod_reset);\n+}\ndiff --git a/include/dt-bindings/reset/altr,rst-mgr-s10.h b/include/dt-bindings/reset/altr,rst-mgr-s10.h\nnew file mode 100644\nindex 0000000..29eb829\n--- /dev/null\n+++ b/include/dt-bindings/reset/altr,rst-mgr-s10.h\n@@ -0,0 +1,97 @@\n+/*\n+ * Copyright (c) 2016-2017 Intel Corporation \n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0\n+ *\n+ */\n+\n+#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H\n+#define _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H\n+\n+/* MPUMODRST */\n+#define CPU0_RESET\t\t0\n+#define CPU1_RESET\t\t1\n+#define CPU2_RESET\t\t2\n+#define CPU3_RESET\t\t3\n+\n+/* PER0MODRST */\n+#define EMAC0_RESET\t\t32\n+#define EMAC1_RESET\t\t33\n+#define EMAC2_RESET\t\t34\n+#define USB0_RESET\t\t35\n+#define USB1_RESET\t\t36\n+#define NAND_RESET\t\t37\n+/* 38 is empty*/\n+#define SDMMC_RESET\t\t39\n+#define EMAC0OCP_RESET\t\t40\n+#define EMAC1OCP_RESET\t\t41\n+#define EMAC2OCP_RESET\t\t42\n+#define USB0OCP_RESET\t\t43\n+#define USB1OCP_RESET\t\t44\n+#define NANDOCP_RESET\t\t45\n+/* 46 is empty*/\n+#define SDMMCOCP_RESET\t\t47\n+#define DMA_RESET\t\t48\n+#define SPIM0_RESET\t\t49\n+#define SPIM1_RESET\t\t50\n+#define SPIS0_RESET\t\t51\n+#define SPIS1_RESET\t\t52\n+#define DMAOCP_RESET\t\t53\n+#define EMACPTP_RESET\t\t54\n+/* 55 is empty*/\n+#define DMAIF0_RESET\t\t56\n+#define DMAIF1_RESET\t\t57\n+#define DMAIF2_RESET\t\t58\n+#define DMAIF3_RESET\t\t59\n+#define DMAIF4_RESET\t\t60\n+#define DMAIF5_RESET\t\t61\n+#define DMAIF6_RESET\t\t62\n+#define DMAIF7_RESET\t\t63\n+\n+/* PER1MODRST */\n+#define L4WD0_RESET\t\t64\n+#define L4WD1_RESET\t\t65\n+#define L4WD2_RESET\t\t66\n+#define L4WD3_RESET\t\t67\n+#define L4SYSTIMER0_RESET\t68\n+#define L4SYSTIMER1_RESET\t69\n+#define SPTIMER0_RESET\t\t70\n+#define SPTIMER1_RESET\t\t71\n+#define I2C0_RESET\t\t72\n+#define I2C1_RESET\t\t73\n+#define I2C2_RESET\t\t74\n+#define I2C3_RESET\t\t75\n+#define I2C4_RESET\t\t76\n+/* 77-79 is reserved */\n+#define UART0_RESET\t\t80\n+#define UART1_RESET\t\t81\n+/* 82-87 is reserved */\n+#define GPIO0_RESET\t\t88\n+#define GPIO1_RESET\t\t89\n+\n+/* BRGMODRST */\n+#define HPS2FPGA_RESET\t\t96\n+#define LWHPS2FPGA_RESET\t97\n+#define FPGA2HPS_RESET\t\t98\n+#define F2SSDRAM0_RESET\t\t99\n+#define F2SSDRAM1_RESET\t\t100\n+#define F2SSDRAM2_RESET\t\t101\n+#define DDRSCH_RESET\t\t102\n+\n+/* 128-159 is reserved */\n+\n+/* COLDMODRST */\n+#define CPUPOR0_RESET\t\t160\n+#define CPUPOR1_RESET\t\t161\n+#define CPUPOR2_RESET\t\t162\n+#define CPUPOR3_RESET\t\t163\n+/* 164-167 is reserved */\n+#define L2_RESET\t\t168\n+\n+/* 192-223 is reserved */\n+\n+/* DBGMODRST */\n+#define DBG_RESET\t\t224\n+#define CSDAP_RESET\t\t225\n+\n+#endif\n","prefixes":["U-Boot","04/14"]}