{"id":815360,"url":"http://patchwork.ozlabs.org/api/patches/815360/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1505812951-25088-3-git-send-email-chin.liang.see@intel.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1505812951-25088-3-git-send-email-chin.liang.see@intel.com>","list_archive_url":null,"date":"2017-09-19T09:22:19","name":"[U-Boot,02/14] arm: dts: Add dts for Stratix10 SoC","commit_ref":null,"pull_url":null,"state":"superseded","archived":false,"hash":"4536e97ae602741965806247500839b4c0650b71","submitter":{"id":70182,"url":"http://patchwork.ozlabs.org/api/people/70182/?format=json","name":"See, Chin Liang","email":"chin.liang.see@intel.com"},"delegate":{"id":1699,"url":"http://patchwork.ozlabs.org/api/users/1699/?format=json","username":"marex","first_name":"Marek","last_name":"Vasut","email":"marek.vasut@gmail.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1505812951-25088-3-git-send-email-chin.liang.see@intel.com/mbox/","series":[{"id":3810,"url":"http://patchwork.ozlabs.org/api/series/3810/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=3810","date":"2017-09-19T09:22:17","name":"Enable Stratix10 SoC support","version":1,"mbox":"http://patchwork.ozlabs.org/series/3810/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/815360/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/815360/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xxHXl0mZzz9ryr\n\tfor ;\n\tTue, 19 Sep 2017 19:25:27 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid C6ACFC21F0E; Tue, 19 Sep 2017 09:24:00 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 46CBAC21ED5;\n\tTue, 19 Sep 2017 09:23:23 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 789DFC21D70; Tue, 19 Sep 2017 09:23:20 +0000 (UTC)","from mga03.intel.com (mga03.intel.com [134.134.136.65])\n\tby lists.denx.de (Postfix) with ESMTPS id E9C66C21D70\n\tfor ; Tue, 19 Sep 2017 09:23:18 +0000 (UTC)","from fmsmga002.fm.intel.com ([10.253.24.26])\n\tby orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t19 Sep 2017 02:23:17 -0700","from pg-interactive1.altera.com ([137.57.137.156])\n\tby fmsmga002.fm.intel.com with ESMTP; 19 Sep 2017 02:22:41 -0700"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-5.0 required=5.0 tests=RCVD_IN_DNSWL_HI\n\tautolearn=unavailable autolearn_force=no version=3.4.0","X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos; i=\"5.42,417,1500966000\"; d=\"scan'208\";\n\ta=\"1220781718\"","From":"chin.liang.see@intel.com","To":"u-boot@lists.denx.de,\n\tMarek Vasut ","Date":"Tue, 19 Sep 2017 17:22:19 +0800","Message-Id":"<1505812951-25088-3-git-send-email-chin.liang.see@intel.com>","X-Mailer":"git-send-email 2.2.2","In-Reply-To":"<1505812951-25088-1-git-send-email-chin.liang.see@intel.com>","References":"<1505812951-25088-1-git-send-email-chin.liang.see@intel.com>","Cc":"Tien Fong Chee ,\n\tChin Liang See ","Subject":"[U-Boot] [PATCH 02/14] arm: dts: Add dts for Stratix10 SoC","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"From: Chin Liang See \n\nDevice tree for Stratix10 SoC\n\nSigned-off-by: Chin Liang See \n---\n arch/arm/dts/Makefile | 3 +-\n arch/arm/dts/socfpga_stratix10_socdk.dts | 141 +++++++++++++++++++++++++++++++\n 2 files changed, 143 insertions(+), 1 deletion(-)\n create mode 100644 arch/arm/dts/socfpga_stratix10_socdk.dts","diff":"diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile\nindex fee4680..4cf5fd0 100644\n--- a/arch/arm/dts/Makefile\n+++ b/arch/arm/dts/Makefile\n@@ -171,7 +171,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=\t\t\t\t\\\n \tsocfpga_cyclone5_sockit.dtb\t\t\t\\\n \tsocfpga_cyclone5_socrates.dtb\t\t\t\\\n \tsocfpga_cyclone5_sr1500.dtb\t\t\t\\\n-\tsocfpga_cyclone5_vining_fpga.dtb\n+\tsocfpga_cyclone5_vining_fpga.dtb\t\t\\\n+\tsocfpga_stratix10_socdk.dtb\n \n dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb\t\\\n \tdra72-evm-revc.dtb dra71-evm.dtb dra76-evm.dtb\ndiff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts\nnew file mode 100644\nindex 0000000..484c630\n--- /dev/null\n+++ b/arch/arm/dts/socfpga_stratix10_socdk.dts\n@@ -0,0 +1,141 @@\n+/*\n+ * Copyright (C) 2016-2017 Intel Corporation \n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0\n+ */\n+\n+/dts-v1/;\n+#include \"skeleton.dtsi\"\n+#include \n+\n+/ {\n+\tmodel = \"Intel SOCFPGA Stratix 10 SoC Development Kit\";\n+\tcompatible = \"altr,socfpga-stratix10\", \"altr,socfpga\";\n+\n+\t#address-cells = <1>;\n+\t#size-cells = <1>;\n+\n+\tchosen {\n+\t\tbootargs = \"console=ttyS0,115200\";\n+\t};\n+\n+\taliases {\n+\t\tethernet0 = &gmac0;\n+\t\tspi0 = &qspi;\n+\t};\n+\n+\tmemory {\n+\t\tname = \"memory\";\n+\t\tdevice_type = \"memory\";\n+\t\treg = <0x0 0x80000000>; /* 2GB */\n+\t};\n+\n+\tregulator_3_3v: 3-3-v-regulator {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"3.3V\";\n+\t\tregulator-min-microvolt = <3300000>;\n+\t\tregulator-max-microvolt = <3300000>;\n+\t};\n+\n+\tsoc {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\tcompatible = \"simple-bus\";\n+\t\tdevice_type = \"soc\";\n+\t\tranges;\n+\t\tu-boot,dm-pre-reloc;\n+\n+\t\trst: rstmgr@ffd11000 {\n+\t\t\t#reset-cells = <1>;\n+\t\t\tcompatible = \"altr,rst-mgr\";\n+\t\t\treg = <0xffd11000 0x100>;\n+\t\t\taltr,modrst-offset = <0x20>;\n+\t\t};\n+\n+\t\tgmac0: ethernet@ff800000 {\n+\t\t\tcompatible = \"altr,socfpga-stmmac\", \"snps,dwmac-3.74a\", \"snps,dwmac\";\n+\t\t\treg = <0xff800000 0x2000>;\n+\t\t\tinterrupts = <0 90 4>;\n+\t\t\tinterrupt-names = \"macirq\";\n+\t\t\tmac-address = [00 00 00 00 00 00];\n+\t\t\tresets = <&rst EMAC0_RESET>;\n+\t\t\treset-names = \"stmmaceth\";\n+\t\t\tphy-mode = \"rgmii\";\n+\t\t\tphy-addr = <0xffffffff>; /* probe for phy addr */\n+\t\t\tmax-speed = <1000>;\n+\t\t\ttxd0-skew-ps = <0>; /* -420ps */\n+\t\t\ttxd1-skew-ps = <0>; /* -420ps */\n+\t\t\ttxd2-skew-ps = <0>; /* -420ps */\n+\t\t\ttxd3-skew-ps = <0>; /* -420ps */\n+\t\t\trxd0-skew-ps = <420>; /* 0ps */\n+\t\t\trxd1-skew-ps = <420>; /* 0ps */\n+\t\t\trxd2-skew-ps = <420>; /* 0ps */\n+\t\t\trxd3-skew-ps = <420>; /* 0ps */\n+\t\t\ttxen-skew-ps = <0>; /* -420ps */\n+\t\t\ttxc-skew-ps = <1860>; /* 960ps */\n+\t\t\trxdv-skew-ps = <420>; /* 0ps */\n+\t\t\trxc-skew-ps = <1680>; /* 780ps */\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\n+\t\tmmc0: dwmmc0@0xff808000 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tcompatible = \"altr,socfpga-dw-mshc\";\n+\t\t\treg = <0xff808000 0x1000>;\n+\t\t\tinterrupts = <0 96 4>;\n+\t\t\tnum-slots = <1>;\n+\t\t\tbroken-cd;\n+\t\t\tbus-width = <4>;\n+\t\t\tfifo-depth = <0x400>;\n+\t\t\tcap-mmc-highspeed;\n+\t\t\tcap-sd-highspeed;\n+\t\t\tdrvsel = <3>;\n+\t\t\tsmplsel = <0>;\n+\t\t\tstatus = \"okay\";\n+\t\t\tu-boot,dm-pre-reloc;\n+\t\t\tvmmc-supply = <®ulator_3_3v>;\n+\t\t\tvqmmc-supply = <®ulator_3_3v>;\n+\t\t};\n+\n+\t\tuart0: serial0@ffc02000 {\n+\t\t\tcompatible = \"snps,dw-apb-uart\";\n+\t\t\treg = <0xffc02000 0x1000>;\n+\t\t\tinterrupts = <0 108 4>;\n+\t\t\treg-shift = <2>;\n+\t\t\treg-io-width = <4>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\n+\t\tqspi: spi@ff8d2000 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tcompatible = \"cadence,qspi\";\n+\t\t\treg = <0xff8d2000 0x100>,\n+\t\t\t\t<0xff900000 0x100000>;\n+\t\t\tinterrupts = <0 98 4>;\n+\t\t\tsram-size = <1024>;\n+\t\t\tbus-num = <0>;\n+\t\t\tspi-max-frequency = <50000000>;\n+\t\t\tspi-tx-bus-width = <1>;\n+\t\t\tspi-rx-bus-width = <4>;\n+\t\t\tstatus = \"okay\";\n+\t\t\tu-boot,dm-pre-reloc;\n+\n+\t\t\tflash0: n25q1024a@0 {\n+\t\t\t\tu-boot,dm-pre-reloc;\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <1>;\n+\t\t\t\tcompatible = \"stmicro,n25q1024a\";\n+\t\t\t\treg = <0>; /* chip select */\n+\t\t\t\tspi-max-frequency = <50000000>;\n+\t\t\t\tpage-size = <256>;\n+\t\t\t\tblock-size = <16>; /* 2^16, 64KB */\n+\t\t\t\ttshsl-ns = <50>;\n+\t\t\t\ttsd2d-ns = <50>;\n+\t\t\t\ttchsh-ns = <4>;\n+\t\t\t\ttslch-ns = <4>;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n","prefixes":["U-Boot","02/14"]}