{"id":815338,"url":"http://patchwork.ozlabs.org/api/patches/815338/?format=json","web_url":"http://patchwork.ozlabs.org/project/netdev/patch/20170919080020.5870-8-jiri@resnulli.us/","project":{"id":7,"url":"http://patchwork.ozlabs.org/api/projects/7/?format=json","name":"Linux network development","link_name":"netdev","list_id":"netdev.vger.kernel.org","list_email":"netdev@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170919080020.5870-8-jiri@resnulli.us>","list_archive_url":null,"date":"2017-09-19T08:00:14","name":"[net-next,07/13] mlxsw: reg: Add the Router Interface Group Version 2 register","commit_ref":null,"pull_url":null,"state":"accepted","archived":true,"hash":"4419eec4614c6659222ead319323c638acff08e7","submitter":{"id":15321,"url":"http://patchwork.ozlabs.org/api/people/15321/?format=json","name":"Jiri Pirko","email":"jiri@resnulli.us"},"delegate":{"id":34,"url":"http://patchwork.ozlabs.org/api/users/34/?format=json","username":"davem","first_name":"David","last_name":"Miller","email":"davem@davemloft.net"},"mbox":"http://patchwork.ozlabs.org/project/netdev/patch/20170919080020.5870-8-jiri@resnulli.us/mbox/","series":[{"id":3798,"url":"http://patchwork.ozlabs.org/api/series/3798/?format=json","web_url":"http://patchwork.ozlabs.org/project/netdev/list/?series=3798","date":"2017-09-19T08:00:07","name":"mlxsw: Prepare for multicast router offload","version":1,"mbox":"http://patchwork.ozlabs.org/series/3798/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/815338/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/815338/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"patchwork-incoming@ozlabs.org","Delivered-To":"patchwork-incoming@ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=resnulli-us.20150623.gappssmtp.com\n\theader.i=@resnulli-us.20150623.gappssmtp.com\n\theader.b=\"zwnFYRUh\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xxFg16yDtz9s7M\n\tfor ;\n\tTue, 19 Sep 2017 18:00:45 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751676AbdISIAn (ORCPT );\n\tTue, 19 Sep 2017 04:00:43 -0400","from mail-wm0-f67.google.com ([74.125.82.67]:37588 \"EHLO\n\tmail-wm0-f67.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751606AbdISIA3 (ORCPT\n\t); Tue, 19 Sep 2017 04:00:29 -0400","by mail-wm0-f67.google.com with SMTP id f4so3039763wmh.4\n\tfor ; Tue, 19 Sep 2017 01:00:29 -0700 (PDT)","from localhost (ip-89-177-125-82.net.upcbroadband.cz.\n\t[89.177.125.82]) by smtp.gmail.com with ESMTPSA id\n\t63sm887380wmm.18.2017.09.19.01.00.28\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tTue, 19 Sep 2017 01:00:28 -0700 (PDT)"],"DKIM-Signature":"v=1; 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The index is to the KVD linear.\n+ * Reserved when vnxet = '0'.\n+ * Access: RW\n+ */\n+MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24);\n+\n+/* reg_rigr2_vrmid\n+ * RMID Index is valid.\n+ * Access: RW\n+ */\n+MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1);\n+\n+/* reg_rigr2_rmid_index\n+ * RMID Index.\n+ * Range 0 .. max_mid - 1\n+ * Reserved when vrmid = '0'.\n+ * The index is to the Port Group Table (PGT)\n+ * Access: RW\n+ */\n+MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16);\n+\n+/* reg_rigr2_erif_entry_v\n+ * Egress Router Interface is valid.\n+ * Note that low-entries must be set if high-entries are set. For\n+ * example: if erif_entry[2].v is set then erif_entry[1].v and\n+ * erif_entry[0].v must be set.\n+ * Index can be from 0 to cap_mc_erif_list_entries-1\n+ * Access: RW\n+ */\n+MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false);\n+\n+/* reg_rigr2_erif_entry_erif\n+ * Egress Router Interface.\n+ * Valid range is from 0 to cap_max_router_interfaces - 1\n+ * Index can be from 0 to MLXSW_REG_RIGR2_MAX_ERIFS - 1\n+ * Access: RW\n+ */\n+MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false);\n+\n+static inline void mlxsw_reg_rigr2_pack(char *payload, u32 rigr_index,\n+\t\t\t\t\tbool vnext, u32 next_rigr_index)\n+{\n+\tMLXSW_REG_ZERO(rigr2, payload);\n+\tmlxsw_reg_rigr2_rigr_index_set(payload, rigr_index);\n+\tmlxsw_reg_rigr2_vnext_set(payload, vnext);\n+\tmlxsw_reg_rigr2_next_rigr_index_set(payload, next_rigr_index);\n+\tmlxsw_reg_rigr2_vrmid_set(payload, 0);\n+\tmlxsw_reg_rigr2_rmid_index_set(payload, 0);\n+}\n+\n+static inline void mlxsw_reg_rigr2_erif_entry_pack(char *payload, int index,\n+\t\t\t\t\t\t bool v, u16 erif)\n+{\n+\tmlxsw_reg_rigr2_erif_entry_v_set(payload, index, v);\n+\tmlxsw_reg_rigr2_erif_entry_erif_set(payload, index, erif);\n+}\n+\n /* MFCR - Management Fan Control Register\n * --------------------------------------\n * This register controls the settings of the Fan Speed PWM mechanism.\n@@ -6917,6 +6999,7 @@ static const struct mlxsw_reg_info *mlxsw_reg_infos[] = {\n \tMLXSW_REG(rauht),\n \tMLXSW_REG(raleu),\n \tMLXSW_REG(rauhtd),\n+\tMLXSW_REG(rigr2),\n \tMLXSW_REG(mfcr),\n \tMLXSW_REG(mfsc),\n \tMLXSW_REG(mfsm),\n","prefixes":["net-next","07/13"]}