{"id":815243,"url":"http://patchwork.ozlabs.org/api/patches/815243/?format=json","web_url":"http://patchwork.ozlabs.org/project/netdev/patch/20170919010628.175732-4-salil.mehta@huawei.com/","project":{"id":7,"url":"http://patchwork.ozlabs.org/api/projects/7/?format=json","name":"Linux network development","link_name":"netdev","list_id":"netdev.vger.kernel.org","list_email":"netdev@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170919010628.175732-4-salil.mehta@huawei.com>","list_archive_url":null,"date":"2017-09-19T01:06:24","name":"[net,3/7] net: hns3: Fix ring and vector map command","commit_ref":null,"pull_url":null,"state":"changes-requested","archived":true,"hash":"a6d522ae4f75ce5916b4f6132c011aa96f8af0d1","submitter":{"id":67454,"url":"http://patchwork.ozlabs.org/api/people/67454/?format=json","name":"Salil Mehta","email":"salil.mehta@huawei.com"},"delegate":{"id":34,"url":"http://patchwork.ozlabs.org/api/users/34/?format=json","username":"davem","first_name":"David","last_name":"Miller","email":"davem@davemloft.net"},"mbox":"http://patchwork.ozlabs.org/project/netdev/patch/20170919010628.175732-4-salil.mehta@huawei.com/mbox/","series":[{"id":3764,"url":"http://patchwork.ozlabs.org/api/series/3764/?format=json","web_url":"http://patchwork.ozlabs.org/project/netdev/list/?series=3764","date":"2017-09-19T01:06:27","name":"Bug fixes for the HNS3 Ethernet Driver for Hip08 SoC","version":1,"mbox":"http://patchwork.ozlabs.org/series/3764/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/815243/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/815243/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"patchwork-incoming@ozlabs.org","Delivered-To":"patchwork-incoming@ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xx4Xz1v1fz9s7B\n\tfor ;\n\tTue, 19 Sep 2017 11:09:55 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751361AbdISBHa (ORCPT );\n\tMon, 18 Sep 2017 21:07:30 -0400","from szxga05-in.huawei.com ([45.249.212.191]:6068 \"EHLO\n\tszxga05-in.huawei.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751283AbdISBH2 (ORCPT\n\t); Mon, 18 Sep 2017 21:07:28 -0400","from 172.30.72.59 (EHLO DGGEMS411-HUB.china.huawei.com)\n\t([172.30.72.59])\n\tby dggrg05-dlp.huawei.com (MOS 4.4.6-GA FastPath queued)\n\twith ESMTP id DHO21277; Tue, 19 Sep 2017 09:07:26 +0800 (CST)","from S00293818-DELL1.china.huawei.com (10.47.92.71) by\n\tDGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP\n\tServer id 14.3.301.0; Tue, 19 Sep 2017 09:07:17 +0800"],"From":"Salil Mehta ","To":"","CC":", ,\n\t, ,\n\t, ,\n\t, ,\n\tMingguang Qu ","Subject":"[PATCH net 3/7] net: hns3: Fix ring and vector map command","Date":"Tue, 19 Sep 2017 02:06:24 +0100","Message-ID":"<20170919010628.175732-4-salil.mehta@huawei.com>","X-Mailer":"git-send-email 2.8.3","In-Reply-To":"<20170919010628.175732-1-salil.mehta@huawei.com>","References":"<20170919010628.175732-1-salil.mehta@huawei.com>","MIME-Version":"1.0","Content-Type":"text/plain","X-Originating-IP":"[10.47.92.71]","X-CFilter-Loop":"Reflected","X-Mirapoint-Virus-RAPID-Raw":"score=unknown(0),\n\trefid=str=0001.0A020206.59C06DCE.00C9, ss=1, re=0.000, recu=0.000,\n\treip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0,\n\tso=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32","X-Mirapoint-Loop-Id":"46f6cb5684d4cc80572216f4a2c60ad6","Sender":"netdev-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"netdev@vger.kernel.org"},"content":"From: Lipeng \n\nThis patch add INT_GL and VF id to vector configure when bind ring\nwith vector. INT_GL means Interrupt Gap Limiting. Vector id starts\nfrom 0 in each VF, so the bind command must specify VF id.\n\nSigned-off-by: Lipeng \nSigned-off-by: Mingguang Qu \nSigned-off-by: Salil Mehta \n---\n drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h | 8 ++++++--\n drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 8 ++++++++\n 2 files changed, 14 insertions(+), 2 deletions(-)","diff":"diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h\nindex 91ae0135ee50..c2b613b40509 100644\n--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h\n+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h\n@@ -238,7 +238,7 @@ struct hclge_tqp_map {\n \tu8 rsv[18];\n };\n \n-#define HCLGE_VECTOR_ELEMENTS_PER_CMD\t11\n+#define HCLGE_VECTOR_ELEMENTS_PER_CMD\t10\n \n enum hclge_int_type {\n \tHCLGE_INT_TX,\n@@ -252,8 +252,12 @@ struct hclge_ctrl_vector_chain {\n #define HCLGE_INT_TYPE_S\t0\n #define HCLGE_INT_TYPE_M\t0x3\n #define HCLGE_TQP_ID_S\t\t2\n-#define HCLGE_TQP_ID_M\t\t(0x3fff << HCLGE_TQP_ID_S)\n+#define HCLGE_TQP_ID_M\t\t(0x7ff << HCLGE_TQP_ID_S)\n+#define HCLGE_INT_GL_IDX_S\t13\n+#define HCLGE_INT_GL_IDX_M\t(0x3 << HCLGE_INT_GL_IDX_S)\n \t__le16 tqp_type_and_id[HCLGE_VECTOR_ELEMENTS_PER_CMD];\n+\tu8 vfid;\n+\tu8 rsv;\n };\n \n #define HCLGE_TC_NUM\t\t8\ndiff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c\nindex e324bc6e9f4f..eafd9c678162 100644\n--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c\n+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c\n@@ -2680,7 +2680,11 @@ int hclge_map_vport_ring_to_vector(struct hclge_vport *vport, int vector_id,\n \t\t\t hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));\n \t\thnae_set_field(req->tqp_type_and_id[i], HCLGE_TQP_ID_M,\n \t\t\t HCLGE_TQP_ID_S,\tnode->tqp_index);\n+\t\thnae_set_field(req->tqp_type_and_id[i], HCLGE_INT_GL_IDX_M,\n+\t\t\t HCLGE_INT_GL_IDX_S,\n+\t\t\t hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));\n \t\treq->tqp_type_and_id[i] = cpu_to_le16(req->tqp_type_and_id[i]);\n+\t\treq->vfid = vport->vport_id;\n \n \t\tif (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {\n \t\t\treq->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;\n@@ -2764,8 +2768,12 @@ static int hclge_unmap_ring_from_vector(\n \t\t\t hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));\n \t\thnae_set_field(req->tqp_type_and_id[i], HCLGE_TQP_ID_M,\n \t\t\t HCLGE_TQP_ID_S,\tnode->tqp_index);\n+\t\thnae_set_field(req->tqp_type_and_id[i], HCLGE_INT_GL_IDX_M,\n+\t\t\t HCLGE_INT_GL_IDX_S,\n+\t\t\t hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));\n \n \t\treq->tqp_type_and_id[i] = cpu_to_le16(req->tqp_type_and_id[i]);\n+\t\treq->vfid = vport->vport_id;\n \n \t\tif (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {\n \t\t\treq->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;\n","prefixes":["net","3/7"]}