{"id":815186,"url":"http://patchwork.ozlabs.org/api/patches/815186/?format=json","web_url":"http://patchwork.ozlabs.org/project/netdev/patch/20170918214128.27896-8-f.fainelli@gmail.com/","project":{"id":7,"url":"http://patchwork.ozlabs.org/api/projects/7/?format=json","name":"Linux network development","link_name":"netdev","list_id":"netdev.vger.kernel.org","list_email":"netdev@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170918214128.27896-8-f.fainelli@gmail.com>","list_archive_url":null,"date":"2017-09-18T21:41:23","name":"[net-next,07/12] net: dsa: b53: Define EEE register page","commit_ref":null,"pull_url":null,"state":"changes-requested","archived":true,"hash":"3ae34bfc89e9e3dc757b13adf176ac2c7a47bbad","submitter":{"id":2800,"url":"http://patchwork.ozlabs.org/api/people/2800/?format=json","name":"Florian Fainelli","email":"f.fainelli@gmail.com"},"delegate":{"id":34,"url":"http://patchwork.ozlabs.org/api/users/34/?format=json","username":"davem","first_name":"David","last_name":"Miller","email":"davem@davemloft.net"},"mbox":"http://patchwork.ozlabs.org/project/netdev/patch/20170918214128.27896-8-f.fainelli@gmail.com/mbox/","series":[{"id":3739,"url":"http://patchwork.ozlabs.org/api/series/3739/?format=json","web_url":"http://patchwork.ozlabs.org/project/netdev/list/?series=3739","date":"2017-09-18T21:41:16","name":"net: dsa: b53/bcm_sf2 cleanups","version":1,"mbox":"http://patchwork.ozlabs.org/series/3739/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/815186/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/815186/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"patchwork-incoming@ozlabs.org","Delivered-To":"patchwork-incoming@ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; 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\n\tMon, 18 Sep 2017 14:41:58 -0700 (PDT)","From":"Florian Fainelli ","To":"netdev@vger.kernel.org","Cc":"davem@davemloft.net, andrew@lunn.ch, vivien.didelot@savoirfairelinux.com,\n\tFlorian Fainelli ","Subject":"[PATCH net-next 07/12] net: dsa: b53: Define EEE register page","Date":"Mon, 18 Sep 2017 14:41:23 -0700","Message-Id":"<20170918214128.27896-8-f.fainelli@gmail.com>","X-Mailer":"git-send-email 2.9.3","In-Reply-To":"<20170918214128.27896-1-f.fainelli@gmail.com>","References":"<20170918214128.27896-1-f.fainelli@gmail.com>","Sender":"netdev-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"netdev@vger.kernel.org"},"content":"In preparation for migrating the EEE code from bcm_sf2 to b53, define the full\nEEE register page and offsets within that page.\n\nSigned-off-by: Florian Fainelli \n---\n drivers/net/dsa/b53/b53_regs.h | 41 +++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 41 insertions(+)","diff":"diff --git a/drivers/net/dsa/b53/b53_regs.h b/drivers/net/dsa/b53/b53_regs.h\nindex 5e8b8e31fee8..2a9f421680aa 100644\n--- a/drivers/net/dsa/b53/b53_regs.h\n+++ b/drivers/net/dsa/b53/b53_regs.h\n@@ -50,6 +50,9 @@\n /* Jumbo Frame Registers */\n #define B53_JUMBO_PAGE\t\t\t0x40\n \n+/* EEE Control Registers Page */\n+#define B53_EEE_PAGE\t\t\t0x92\n+\n /* CFP Configuration Registers Page */\n #define B53_CFP_PAGE\t\t\t0xa1\n \n@@ -472,6 +475,44 @@\n #define JMS_MAX_SIZE\t\t\t9724\n \n /*************************************************************************\n+ * EEE Configuration Page Registers\n+ *************************************************************************/\n+\n+/* EEE Enable control register (16 bit) */\n+#define B53_EEE_EN_CTRL\t\t\t0x00\n+\n+/* EEE LPI assert status register (16 bit) */\n+#define B53_EEE_LPI_ASSERT_STS\t\t0x02\n+\n+/* EEE LPI indicate status register (16 bit) */\n+#define B53_EEE_LPI_INDICATE\t\t0x4\n+\n+/* EEE Receiving idle symbols status register (16 bit) */\n+#define B53_EEE_RX_IDLE_SYM_STS\t\t0x6\n+\n+/* EEE Pipeline timer register (32 bit) */\n+#define B53_EEE_PIP_TIMER\t\t0xC\n+\n+/* EEE Sleep timer Gig register (32 bit) */\n+#define B53_EEE_SLEEP_TIMER_GIG(i)\t(0x10 + 4 * (i))\n+\n+/* EEE Sleep timer FE register (32 bit) */\n+#define B53_EEE_SLEEP_TIMER_FE(i)\t(0x34 + 4 * (i))\n+\n+/* EEE Minimum LP timer Gig register (32 bit) */\n+#define B53_EEE_MIN_LP_TIMER_GIG(i)\t(0x58 + 4 * (i))\n+\n+/* EEE Minimum LP timer FE register (32 bit) */\n+#define B53_EEE_MIN_LP_TIMER_FE(i)\t(0x7c + 4 * (i))\n+\n+/* EEE Wake timer Gig register (16 bit) */\n+#define B53_EEE_WAKE_TIMER_GIG(i)\t(0xa0 + 2 * (i))\n+\n+/* EEE Wake timer FE register (16 bit) */\n+#define B53_EEE_WAKE_TIMER_FE(i)\t(0xb2 + 2 * (i))\n+\n+\n+/*************************************************************************\n * CFP Configuration Page Registers\n *************************************************************************/\n \n","prefixes":["net-next","07/12"]}