{"id":815167,"url":"http://patchwork.ozlabs.org/api/patches/815167/?format=json","web_url":"http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1505767187-4596-9-git-send-email-roy.pledge@nxp.com/","project":{"id":2,"url":"http://patchwork.ozlabs.org/api/projects/2/?format=json","name":"Linux PPC development","link_name":"linuxppc-dev","list_id":"linuxppc-dev.lists.ozlabs.org","list_email":"linuxppc-dev@lists.ozlabs.org","web_url":"https://github.com/linuxppc/wiki/wiki","scm_url":"https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git","webscm_url":"https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/","list_archive_url":"https://lore.kernel.org/linuxppc-dev/","list_archive_url_format":"https://lore.kernel.org/linuxppc-dev/{}/","commit_url_format":"https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}"},"msgid":"<1505767187-4596-9-git-send-email-roy.pledge@nxp.com>","list_archive_url":"https://lore.kernel.org/linuxppc-dev/1505767187-4596-9-git-send-email-roy.pledge@nxp.com/","date":"2017-09-18T20:39:43","name":"[v5,08/12] soc/fsl/qbman: Rework portal mapping calls for ARM/PPC","commit_ref":null,"pull_url":null,"state":"not-applicable","archived":false,"hash":"cdf77964be8338d3e2e7eddef471f1299767a0cd","submitter":{"id":70252,"url":"http://patchwork.ozlabs.org/api/people/70252/?format=json","name":"Roy Pledge","email":"roy.pledge@nxp.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1505767187-4596-9-git-send-email-roy.pledge@nxp.com/mbox/","series":[{"id":3731,"url":"http://patchwork.ozlabs.org/api/series/3731/?format=json","web_url":"http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=3731","date":"2017-09-18T20:39:38","name":"soc/fsl/qbman: Enable QBMan on ARM Platforms","version":5,"mbox":"http://patchwork.ozlabs.org/series/3731/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/815167/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/815167/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xwywG4Tswz9s7m\n\tfor ;\n\tTue, 19 Sep 2017 06:56:14 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xwywG3ctgzDqYP\n\tfor ;\n\tTue, 19 Sep 2017 06:56:14 +1000 (AEST)","from NAM03-CO1-obe.outbound.protection.outlook.com\n\t(mail-co1nam03on0604.outbound.protection.outlook.com\n\t[IPv6:2a01:111:f400:fe48::604])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xwyYc0fVpzDq78\n\tfor ;\n\tTue, 19 Sep 2017 06:40:03 +1000 (AEST)","from BN3PR03CA0090.namprd03.prod.outlook.com (10.167.1.178) by\n\tBN6PR03MB2689.namprd03.prod.outlook.com (10.173.144.8) with Microsoft\n\tSMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id\n\t15.20.56.11; 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PCL:0;\n\tRULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(400006)(100000804101)(100110200095)(100000805101)(100110500095);\n\tSRVR:BN6PR03MB2689; ","X-Forefront-PRVS":"04347F8039","SpamDiagnosticOutput":"1:99","SpamDiagnosticMetadata":"NSPM","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"18 Sep 2017 20:39:58.6891\n\t(UTC)","X-MS-Exchange-CrossTenant-Id":"5afe0b00-7697-4969-b663-5eab37d5f47e","X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp":"TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e;\n\tIp=[192.88.168.50]; \n\tHelo=[tx30smr01.am.freescale.net]","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"BN6PR03MB2689","X-BeenThere":"linuxppc-dev@lists.ozlabs.org","X-Mailman-Version":"2.1.24","Precedence":"list","List-Id":"Linux on PowerPC Developers Mail List\n\t","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Reply-To":"roy.pledge@nxp.com","Cc":"mark.rutland@arm.com, arnd@arndb.de, madalin.bucur@nxp.com,\n\tcatalin.marinas@arm.com, Roy Pledge ,\n\tlinux@armlinux.org.uk, oss@buserror.net","Errors-To":"linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org","Sender":"\"Linuxppc-dev\"\n\t"},"content":"Rework portal mapping for PPC and ARM. The PPC devices require a\ncacheable coherent mapping while ARM will work with a non-cachable/write\ncombine mapping. This also eliminates the need for manual cache\nflushes on ARM. This also fixes the code so sparse checking is clean.\n\nSigned-off-by: Roy Pledge \n---\n drivers/soc/fsl/qbman/bman.c | 18 ++++++++++--------\n drivers/soc/fsl/qbman/bman_portal.c | 23 ++++++++++-------------\n drivers/soc/fsl/qbman/bman_priv.h | 8 +++-----\n drivers/soc/fsl/qbman/dpaa_sys.h | 15 +++++++++++----\n drivers/soc/fsl/qbman/qman.c | 31 +++++++++++++------------------\n drivers/soc/fsl/qbman/qman_portal.c | 23 ++++++++++-------------\n drivers/soc/fsl/qbman/qman_priv.h | 8 +++-----\n 7 files changed, 60 insertions(+), 66 deletions(-)","diff":"diff --git a/drivers/soc/fsl/qbman/bman.c b/drivers/soc/fsl/qbman/bman.c\nindex ff8998f..5dbb5cc 100644\n--- a/drivers/soc/fsl/qbman/bman.c\n+++ b/drivers/soc/fsl/qbman/bman.c\n@@ -154,7 +154,8 @@ struct bm_mc {\n };\n \n struct bm_addr {\n-\tvoid __iomem *ce;\t/* cache-enabled */\n+\tvoid *ce;\t\t/* cache-enabled */\n+\t__be32 *ce_be;\t\t/* Same as above but for direct access */\n \tvoid __iomem *ci;\t/* cache-inhibited */\n };\n \n@@ -167,12 +168,12 @@ struct bm_portal {\n /* Cache-inhibited register access. */\n static inline u32 bm_in(struct bm_portal *p, u32 offset)\n {\n-\treturn be32_to_cpu(__raw_readl(p->addr.ci + offset));\n+\treturn ioread32be(p->addr.ci + offset);\n }\n \n static inline void bm_out(struct bm_portal *p, u32 offset, u32 val)\n {\n-\t__raw_writel(cpu_to_be32(val), p->addr.ci + offset);\n+\tiowrite32be(val, p->addr.ci + offset);\n }\n \n /* Cache Enabled Portal Access */\n@@ -188,7 +189,7 @@ static inline void bm_cl_touch_ro(struct bm_portal *p, u32 offset)\n \n static inline u32 bm_ce_in(struct bm_portal *p, u32 offset)\n {\n-\treturn be32_to_cpu(__raw_readl(p->addr.ce + offset));\n+\treturn be32_to_cpu(*(p->addr.ce_be + (offset/4)));\n }\n \n struct bman_portal {\n@@ -408,7 +409,7 @@ static int bm_mc_init(struct bm_portal *portal)\n \n \tmc->cr = portal->addr.ce + BM_CL_CR;\n \tmc->rr = portal->addr.ce + BM_CL_RR0;\n-\tmc->rridx = (__raw_readb(&mc->cr->_ncw_verb) & BM_MCC_VERB_VBIT) ?\n+\tmc->rridx = (mc->cr->_ncw_verb & BM_MCC_VERB_VBIT) ?\n \t\t 0 : 1;\n \tmc->vbit = mc->rridx ? BM_MCC_VERB_VBIT : 0;\n #ifdef CONFIG_FSL_DPAA_CHECKING\n@@ -466,7 +467,7 @@ static inline union bm_mc_result *bm_mc_result(struct bm_portal *portal)\n \t * its command is submitted and completed. This includes the valid-bit,\n \t * in case you were wondering...\n \t */\n-\tif (!__raw_readb(&rr->verb)) {\n+\tif (!rr->verb) {\n \t\tdpaa_invalidate_touch_ro(rr);\n \t\treturn NULL;\n \t}\n@@ -512,8 +513,9 @@ static int bman_create_portal(struct bman_portal *portal,\n \t * config, everything that follows depends on it and \"config\" is more\n \t * for (de)reference...\n \t */\n-\tp->addr.ce = c->addr_virt[DPAA_PORTAL_CE];\n-\tp->addr.ci = c->addr_virt[DPAA_PORTAL_CI];\n+\tp->addr.ce = c->addr_virt_ce;\n+\tp->addr.ce_be = c->addr_virt_ce;\n+\tp->addr.ci = c->addr_virt_ci;\n \tif (bm_rcr_init(p, bm_rcr_pvb, bm_rcr_cce)) {\n \t\tdev_err(c->dev, \"RCR initialisation failed\\n\");\n \t\tgoto fail_rcr;\ndiff --git a/drivers/soc/fsl/qbman/bman_portal.c b/drivers/soc/fsl/qbman/bman_portal.c\nindex 39b39c8..2f71f7d 100644\n--- a/drivers/soc/fsl/qbman/bman_portal.c\n+++ b/drivers/soc/fsl/qbman/bman_portal.c\n@@ -91,7 +91,6 @@ static int bman_portal_probe(struct platform_device *pdev)\n \tstruct device_node *node = dev->of_node;\n \tstruct bm_portal_config *pcfg;\n \tstruct resource *addr_phys[2];\n-\tvoid __iomem *va;\n \tint irq, cpu;\n \n \tpcfg = devm_kmalloc(dev, sizeof(*pcfg), GFP_KERNEL);\n@@ -123,23 +122,21 @@ static int bman_portal_probe(struct platform_device *pdev)\n \t}\n \tpcfg->irq = irq;\n \n-\tva = ioremap_prot(addr_phys[0]->start, resource_size(addr_phys[0]), 0);\n-\tif (!va) {\n-\t\tdev_err(dev, \"ioremap::CE failed\\n\");\n+\tpcfg->addr_virt_ce = memremap(addr_phys[0]->start,\n+\t\t\t\t\tresource_size(addr_phys[0]),\n+\t\t\t\t\tQBMAN_MEMREMAP_ATTR);\n+\tif (!pcfg->addr_virt_ce) {\n+\t\tdev_err(dev, \"memremap::CE failed\\n\");\n \t\tgoto err_ioremap1;\n \t}\n \n-\tpcfg->addr_virt[DPAA_PORTAL_CE] = va;\n-\n-\tva = ioremap_prot(addr_phys[1]->start, resource_size(addr_phys[1]),\n-\t\t\t _PAGE_GUARDED | _PAGE_NO_CACHE);\n-\tif (!va) {\n+\tpcfg->addr_virt_ci = ioremap(addr_phys[1]->start,\n+\t\t\t\t\tresource_size(addr_phys[1]));\n+\tif (!pcfg->addr_virt_ci) {\n \t\tdev_err(dev, \"ioremap::CI failed\\n\");\n \t\tgoto err_ioremap2;\n \t}\n \n-\tpcfg->addr_virt[DPAA_PORTAL_CI] = va;\n-\n \tspin_lock(&bman_lock);\n \tcpu = cpumask_next_zero(-1, &portal_cpus);\n \tif (cpu >= nr_cpu_ids) {\n@@ -164,9 +161,9 @@ static int bman_portal_probe(struct platform_device *pdev)\n \treturn 0;\n \n err_portal_init:\n-\tiounmap(pcfg->addr_virt[DPAA_PORTAL_CI]);\n+\tiounmap(pcfg->addr_virt_ci);\n err_ioremap2:\n-\tiounmap(pcfg->addr_virt[DPAA_PORTAL_CE]);\n+\tmemunmap(pcfg->addr_virt_ce);\n err_ioremap1:\n \treturn -ENXIO;\n }\ndiff --git a/drivers/soc/fsl/qbman/bman_priv.h b/drivers/soc/fsl/qbman/bman_priv.h\nindex f6896a2..751ce90 100644\n--- a/drivers/soc/fsl/qbman/bman_priv.h\n+++ b/drivers/soc/fsl/qbman/bman_priv.h\n@@ -46,11 +46,9 @@ extern u16 bman_ip_rev;\t/* 0 if uninitialised, otherwise BMAN_REVx */\n extern struct gen_pool *bm_bpalloc;\n \n struct bm_portal_config {\n-\t/*\n-\t * Corenet portal addresses;\n-\t * [0]==cache-enabled, [1]==cache-inhibited.\n-\t */\n-\tvoid __iomem *addr_virt[2];\n+\t/* Portal addresses */\n+\tvoid *addr_virt_ce;\n+\tvoid __iomem *addr_virt_ci;\n \t/* Allow these to be joined in lists */\n \tstruct list_head list;\n \tstruct device *dev;\ndiff --git a/drivers/soc/fsl/qbman/dpaa_sys.h b/drivers/soc/fsl/qbman/dpaa_sys.h\nindex 61cfdb3..5a2c0af 100644\n--- a/drivers/soc/fsl/qbman/dpaa_sys.h\n+++ b/drivers/soc/fsl/qbman/dpaa_sys.h\n@@ -51,12 +51,12 @@\n \n static inline void dpaa_flush(void *p)\n {\n+\t/*\n+\t * Only PPC needs to flush the cache currently - on ARM the mapping\n+\t * is non cacheable\n+\t */\n #ifdef CONFIG_PPC\n \tflush_dcache_range((unsigned long)p, (unsigned long)p+64);\n-#elif defined(CONFIG_ARM)\n-\t__cpuc_flush_dcache_area(p, 64);\n-#elif defined(CONFIG_ARM64)\n-\t__flush_dcache_area(p, 64);\n #endif\n }\n \n@@ -102,4 +102,11 @@ static inline u8 dpaa_cyc_diff(u8 ringsize, u8 first, u8 last)\n int qbman_init_private_mem(struct device *dev, int idx, dma_addr_t *addr,\n \t\t\t\tsize_t *size);\n \n+/* memremap() attributes for different platforms */\n+#ifdef CONFIG_PPC\n+#define QBMAN_MEMREMAP_ATTR\tMEMREMAP_WB\n+#else\n+#define QBMAN_MEMREMAP_ATTR\tMEMREMAP_WC\n+#endif\n+\n #endif\t/* __DPAA_SYS_H */\ndiff --git a/drivers/soc/fsl/qbman/qman.c b/drivers/soc/fsl/qbman/qman.c\nindex 25419e1..8934c27 100644\n--- a/drivers/soc/fsl/qbman/qman.c\n+++ b/drivers/soc/fsl/qbman/qman.c\n@@ -300,7 +300,8 @@ struct qm_mc {\n };\n \n struct qm_addr {\n-\tvoid __iomem *ce;\t/* cache-enabled */\n+\tvoid *ce;\t\t/* cache-enabled */\n+\t__be32 *ce_be;\t\t/* same value as above but for direct access */\n \tvoid __iomem *ci;\t/* cache-inhibited */\n };\n \n@@ -321,12 +322,12 @@ struct qm_portal {\n /* Cache-inhibited register access. */\n static inline u32 qm_in(struct qm_portal *p, u32 offset)\n {\n-\treturn be32_to_cpu(__raw_readl(p->addr.ci + offset));\n+\treturn ioread32be(p->addr.ci + offset);\n }\n \n static inline void qm_out(struct qm_portal *p, u32 offset, u32 val)\n {\n-\t__raw_writel(cpu_to_be32(val), p->addr.ci + offset);\n+\tiowrite32be(val, p->addr.ci + offset);\n }\n \n /* Cache Enabled Portal Access */\n@@ -342,7 +343,7 @@ static inline void qm_cl_touch_ro(struct qm_portal *p, u32 offset)\n \n static inline u32 qm_ce_in(struct qm_portal *p, u32 offset)\n {\n-\treturn be32_to_cpu(__raw_readl(p->addr.ce + offset));\n+\treturn be32_to_cpu(*(p->addr.ce_be + (offset/4)));\n }\n \n /* --- EQCR API --- */\n@@ -646,11 +647,7 @@ static inline void qm_dqrr_pvb_update(struct qm_portal *portal)\n \t */\n \tdpaa_invalidate_touch_ro(res);\n #endif\n-\t/*\n-\t * when accessing 'verb', use __raw_readb() to ensure that compiler\n-\t * inlining doesn't try to optimise out \"excess reads\".\n-\t */\n-\tif ((__raw_readb(&res->verb) & QM_DQRR_VERB_VBIT) == dqrr->vbit) {\n+\tif ((res->verb & QM_DQRR_VERB_VBIT) == dqrr->vbit) {\n \t\tdqrr->pi = (dqrr->pi + 1) & (QM_DQRR_SIZE - 1);\n \t\tif (!dqrr->pi)\n \t\t\tdqrr->vbit ^= QM_DQRR_VERB_VBIT;\n@@ -777,11 +774,8 @@ static inline void qm_mr_pvb_update(struct qm_portal *portal)\n \tunion qm_mr_entry *res = qm_cl(mr->ring, mr->pi);\n \n \tDPAA_ASSERT(mr->pmode == qm_mr_pvb);\n-\t/*\n-\t * when accessing 'verb', use __raw_readb() to ensure that compiler\n-\t * inlining doesn't try to optimise out \"excess reads\".\n-\t */\n-\tif ((__raw_readb(&res->verb) & QM_MR_VERB_VBIT) == mr->vbit) {\n+\n+\tif ((res->verb & QM_MR_VERB_VBIT) == mr->vbit) {\n \t\tmr->pi = (mr->pi + 1) & (QM_MR_SIZE - 1);\n \t\tif (!mr->pi)\n \t\t\tmr->vbit ^= QM_MR_VERB_VBIT;\n@@ -822,7 +816,7 @@ static inline int qm_mc_init(struct qm_portal *portal)\n \n \tmc->cr = portal->addr.ce + QM_CL_CR;\n \tmc->rr = portal->addr.ce + QM_CL_RR0;\n-\tmc->rridx = (__raw_readb(&mc->cr->_ncw_verb) & QM_MCC_VERB_VBIT)\n+\tmc->rridx = (mc->cr->_ncw_verb & QM_MCC_VERB_VBIT)\n \t\t ? 0 : 1;\n \tmc->vbit = mc->rridx ? QM_MCC_VERB_VBIT : 0;\n #ifdef CONFIG_FSL_DPAA_CHECKING\n@@ -880,7 +874,7 @@ static inline union qm_mc_result *qm_mc_result(struct qm_portal *portal)\n \t * its command is submitted and completed. This includes the valid-bit,\n \t * in case you were wondering...\n \t */\n-\tif (!__raw_readb(&rr->verb)) {\n+\tif (!rr->verb) {\n \t\tdpaa_invalidate_touch_ro(rr);\n \t\treturn NULL;\n \t}\n@@ -1123,8 +1117,9 @@ static int qman_create_portal(struct qman_portal *portal,\n \t * config, everything that follows depends on it and \"config\" is more\n \t * for (de)reference\n \t */\n-\tp->addr.ce = c->addr_virt[DPAA_PORTAL_CE];\n-\tp->addr.ci = c->addr_virt[DPAA_PORTAL_CI];\n+\tp->addr.ce = c->addr_virt_ce;\n+\tp->addr.ce_be = c->addr_virt_ce;\n+\tp->addr.ci = c->addr_virt_ci;\n \t/*\n \t * If CI-stashing is used, the current defaults use a threshold of 3,\n \t * and stash with high-than-DQRR priority.\ndiff --git a/drivers/soc/fsl/qbman/qman_portal.c b/drivers/soc/fsl/qbman/qman_portal.c\nindex cbacdf4..a120002 100644\n--- a/drivers/soc/fsl/qbman/qman_portal.c\n+++ b/drivers/soc/fsl/qbman/qman_portal.c\n@@ -224,7 +224,6 @@ static int qman_portal_probe(struct platform_device *pdev)\n \tstruct device_node *node = dev->of_node;\n \tstruct qm_portal_config *pcfg;\n \tstruct resource *addr_phys[2];\n-\tvoid __iomem *va;\n \tint irq, cpu, err;\n \tu32 val;\n \n@@ -262,23 +261,21 @@ static int qman_portal_probe(struct platform_device *pdev)\n \t}\n \tpcfg->irq = irq;\n \n-\tva = ioremap_prot(addr_phys[0]->start, resource_size(addr_phys[0]), 0);\n-\tif (!va) {\n-\t\tdev_err(dev, \"ioremap::CE failed\\n\");\n+\tpcfg->addr_virt_ce = memremap(addr_phys[0]->start,\n+\t\t\t\t\tresource_size(addr_phys[0]),\n+\t\t\t\t\tQBMAN_MEMREMAP_ATTR);\n+\tif (!pcfg->addr_virt_ce) {\n+\t\tdev_err(dev, \"memremap::CE failed\\n\");\n \t\tgoto err_ioremap1;\n \t}\n \n-\tpcfg->addr_virt[DPAA_PORTAL_CE] = va;\n-\n-\tva = ioremap_prot(addr_phys[1]->start, resource_size(addr_phys[1]),\n-\t\t\t _PAGE_GUARDED | _PAGE_NO_CACHE);\n-\tif (!va) {\n+\tpcfg->addr_virt_ci = ioremap(addr_phys[1]->start,\n+\t\t\t\tresource_size(addr_phys[1]));\n+\tif (!pcfg->addr_virt_ci) {\n \t\tdev_err(dev, \"ioremap::CI failed\\n\");\n \t\tgoto err_ioremap2;\n \t}\n \n-\tpcfg->addr_virt[DPAA_PORTAL_CI] = va;\n-\n \tpcfg->pools = qm_get_pools_sdqcr();\n \n \tspin_lock(&qman_lock);\n@@ -310,9 +307,9 @@ static int qman_portal_probe(struct platform_device *pdev)\n \treturn 0;\n \n err_portal_init:\n-\tiounmap(pcfg->addr_virt[DPAA_PORTAL_CI]);\n+\tiounmap(pcfg->addr_virt_ci);\n err_ioremap2:\n-\tiounmap(pcfg->addr_virt[DPAA_PORTAL_CE]);\n+\tmemunmap(pcfg->addr_virt_ce);\n err_ioremap1:\n \treturn -ENXIO;\n }\ndiff --git a/drivers/soc/fsl/qbman/qman_priv.h b/drivers/soc/fsl/qbman/qman_priv.h\nindex b1e2cbf..9407d2e 100644\n--- a/drivers/soc/fsl/qbman/qman_priv.h\n+++ b/drivers/soc/fsl/qbman/qman_priv.h\n@@ -153,11 +153,9 @@ static inline void qman_cgrs_xor(struct qman_cgrs *dest,\n void qman_init_cgr_all(void);\n \n struct qm_portal_config {\n-\t/*\n-\t * Corenet portal addresses;\n-\t * [0]==cache-enabled, [1]==cache-inhibited.\n-\t */\n-\tvoid __iomem *addr_virt[2];\n+\t/* Portal addresses */\n+\tvoid *addr_virt_ce;\n+\tvoid __iomem *addr_virt_ci;\n \tstruct device *dev;\n \tstruct iommu_domain *iommu_domain;\n \t/* Allow these to be joined in lists */\n","prefixes":["v5","08/12"]}