{"id":814943,"url":"http://patchwork.ozlabs.org/api/patches/814943/?format=json","web_url":"http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20170918134610.17743-3-jbrunet@baylibre.com/","project":{"id":37,"url":"http://patchwork.ozlabs.org/api/projects/37/?format=json","name":"Devicetree Bindings","link_name":"devicetree-bindings","list_id":"devicetree.vger.kernel.org","list_email":"devicetree@vger.kernel.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170918134610.17743-3-jbrunet@baylibre.com>","list_archive_url":null,"date":"2017-09-18T13:46:09","name":"[v4,1/2] dt-bindings: interrupt-controller: add DT binding for meson GPIO interrupt controller","commit_ref":null,"pull_url":null,"state":"not-applicable","archived":true,"hash":"98422ce3c4ac6274e58a23a15596e70eb97e7662","submitter":{"id":69839,"url":"http://patchwork.ozlabs.org/api/people/69839/?format=json","name":"Jerome Brunet","email":"jbrunet@baylibre.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20170918134610.17743-3-jbrunet@baylibre.com/mbox/","series":[{"id":3650,"url":"http://patchwork.ozlabs.org/api/series/3650/?format=json","web_url":"http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=3650","date":"2017-09-18T13:46:07","name":"irqchip: meson: add support for the gpio interrupt controller","version":4,"mbox":"http://patchwork.ozlabs.org/series/3650/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/814943/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/814943/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=baylibre-com.20150623.gappssmtp.com\n\theader.i=@baylibre-com.20150623.gappssmtp.com header.b=\"Gz4J7cW7\"; \n\tdkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xwnRg1sJvz9s7c\n\tfor ;\n\tMon, 18 Sep 2017 23:49:19 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1754003AbdIRNqs (ORCPT\n\t);\n\tMon, 18 Sep 2017 09:46:48 -0400","from mail-wr0-f180.google.com ([209.85.128.180]:46612 \"EHLO\n\tmail-wr0-f180.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S932688AbdIRNqR (ORCPT\n\t); Mon, 18 Sep 2017 09:46:17 -0400","by mail-wr0-f180.google.com with SMTP id o42so540383wrb.3\n\tfor ;\n\tMon, 18 Sep 2017 06:46:16 -0700 (PDT)","from localhost.localdomain ([90.63.244.31])\n\tby smtp.googlemail.com with ESMTPSA id\n\tn29sm6888585wmi.46.2017.09.18.06.46.15\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tMon, 18 Sep 2017 06:46:15 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=baylibre-com.20150623.gappssmtp.com; s=20150623;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references\n\t:mime-version:content-transfer-encoding;\n\tbh=r/zvGjiMzT2GM5av7cyQS7Gvu/XjANYw4OUvXWzraqM=;\n\tb=Gz4J7cW7LZO0xc06fhEn+XUe2tSkDmro7y0EkjWaWxlNb1ws5lcD8XM5qsQK9eHaD/\n\tOaY5GNcGIV0OhBB0S7Px9DaxouRBUNU5OgjgmIIsN459gRNV3+R2JHr3EoA0GbIv3k+o\n\tM0Ry0cXGe3PT91vryVZtXgtsFpm3YRgx9QFDarPvNmXsPDvc1rkw285xU0Um0hNu2aTh\n\t7vlL2ewD1/qjfRwJ/+eGQmQPv6+2Fue97LEqPncqwYLU5bIXNSBLh64msluqc5hIGEVl\n\tATPUBMva3VQAXXQ5MReQ92Vwvekj4Fn/yzFcbi2F8CSkcthjbuKKIQqTMjMdNK5in2d1\n\t6YAg==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-transfer-encoding;\n\tbh=r/zvGjiMzT2GM5av7cyQS7Gvu/XjANYw4OUvXWzraqM=;\n\tb=nPtyF+Q9y8uHjnbfl+AKyWfZf6GxeAncYwAJw5U8kozL+pqGy7YKfI4dH+NS3p/3qm\n\tiTRuB+DEb7lIkHUZ61zRK2GO1LJw1g97bTPxU4PXJB8b8GkEh9VNFLddrBjoOO5HmyWu\n\tnB7BW/HHRU9iuTlRu6ZfM7kqm5GLydQ2Gdf4x824L0DBveXzzgTD0XvMd49t2w7DNSHx\n\tr6QgdIJIlSs988gLRRrCHGZmwIssCq7pG0BBhvC/A6noRIHVp0EQbPkUD2QYVWNYd37X\n\tvS3zV74b7xw0vTO78kOuNXGGaN2DNJog6M25ZQlbDnXPZVJ2D7Fel2NOWihdzkMM2cJg\n\tQ3NA==","X-Gm-Message-State":"AHPjjUjLkbkmc8ov/A9ENNeeY3OjgJqEKUhWhd4fDR7XUZzQXipDqlei\n\tMuE0sCD3M2Xp4Z7T","X-Google-Smtp-Source":"AOwi7QD7NhV5zDbzrJbhH/J0yNIThvodOAkN/cYBtvwszYIEe7VxbvR7gGNkAWtzwQ9mcAg/LuDHJQ==","X-Received":"by 10.223.161.137 with SMTP id u9mr14967752wru.280.1505742376200;\n\tMon, 18 Sep 2017 06:46:16 -0700 (PDT)","From":"Jerome Brunet ","To":"Marc Zyngier , Thomas Gleixner ,\n\tJason Cooper ,\n\tHeiner Kallweit ","Cc":"Jerome Brunet , Kevin Hilman ,\n\tCarlo Caione , linux-amlogic@lists.infradead.org,\n\tlinux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org","Subject":"[PATCH v4 1/2] dt-bindings: interrupt-controller: add DT binding for\n\tmeson GPIO interrupt controller","Date":"Mon, 18 Sep 2017 15:46:09 +0200","Message-Id":"<20170918134610.17743-3-jbrunet@baylibre.com>","X-Mailer":"git-send-email 2.13.5","In-Reply-To":"<20170918134610.17743-1-jbrunet@baylibre.com>","References":"<20170918134610.17743-1-jbrunet@baylibre.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"8bit","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"},"content":"This commit adds the device tree bindings description for Amlogic's GPIO\ninterrupt controller available on the meson8b, gxbb and gxl SoC families\n\nCc: Heiner Kallweit \nSigned-off-by: Jerome Brunet \n---\n .../amlogic,meson-gpio-intc.txt | 35 ++++++++++++++++++++++\n 1 file changed, 35 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt","diff":"diff --git a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt\nnew file mode 100644\nindex 000000000000..633e21ce4b17\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt\n@@ -0,0 +1,35 @@\n+Amlogic meson GPIO interrupt controller\n+\n+Meson SoCs contains an interrupt controller which is able to watch the SoC\n+pads and generate an interrupt on edge or level. The controller is essentially\n+a 256 pads to 8 GIC interrupt multiplexer, with a filter block to select edge\n+or level and polarity. It does not expose all 256 mux inputs because the\n+documentation shows that the upper part is not mapped to any pad. The actual\n+number of interrupt exposed depends on the SoC.\n+\n+Required properties:\n+\n+- compatible : must have \"amlogic,meson8-gpio-intc” and either\n+ “amlogic,meson8b-gpio-intc” for meson8b SoCs (S805) or\n+ “amlogic,meson-gxbb-gpio-intc” for GXBB SoCs (S905) or\n+ “amlogic,meson-gxl-gpio-intc” for GXL SoCs (S905X, S912)\n+- interrupt-parent : a phandle to the GIC the interrupts are routed to.\n+ Usually this is provided at the root level of the device tree as it is\n+ common to most of the SoC.\n+- reg : Specifies base physical address and size of the registers.\n+- interrupt-controller : Identifies the node as an interrupt controller.\n+- #interrupt-cells : Specifies the number of cells needed to encode an\n+ interrupt source. The value must be 2.\n+- meson,channel-interrupts: Array with the 8 upstream hwirq numbers. These\n+ are the hwirqs used on the parent interrupt controller.\n+\n+Example:\n+\n+gpio_interrupt: interrupt-controller@9880 {\n+\tcompatible = \"amlogic,meson-gxbb-gpio-intc\",\n+\t\t \"amlogic,meson-gpio-intc\";\n+\treg = <0x0 0x9880 0x0 0x10>;\n+\tinterrupt-controller;\n+\t#interrupt-cells = <2>;\n+\tmeson,channel-interrupts = <64 65 66 67 68 69 70 71>;\n+};\n","prefixes":["v4","1/2"]}