{"id":814941,"url":"http://patchwork.ozlabs.org/api/patches/814941/?format=json","web_url":"http://patchwork.ozlabs.org/project/devicetree-bindings/patch/1505742407-31576-2-git-send-email-geert+renesas@glider.be/","project":{"id":37,"url":"http://patchwork.ozlabs.org/api/projects/37/?format=json","name":"Devicetree Bindings","link_name":"devicetree-bindings","list_id":"devicetree.vger.kernel.org","list_email":"devicetree@vger.kernel.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1505742407-31576-2-git-send-email-geert+renesas@glider.be>","list_archive_url":null,"date":"2017-09-18T13:46:41","name":"[v3,1/7] dt-bindings: timer: renesas, cmt: Fix SoC-specific compatible values","commit_ref":null,"pull_url":null,"state":"not-applicable","archived":true,"hash":"d962f0bbcccf91b947cb471e1ccade9aa962c114","submitter":{"id":63808,"url":"http://patchwork.ozlabs.org/api/people/63808/?format=json","name":"Geert Uytterhoeven","email":"geert+renesas@glider.be"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/devicetree-bindings/patch/1505742407-31576-2-git-send-email-geert+renesas@glider.be/mbox/","series":[{"id":3652,"url":"http://patchwork.ozlabs.org/api/series/3652/?format=json","web_url":"http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=3652","date":"2017-09-18T13:46:41","name":"clocksource: sh_cmt: Update driver for DT binding rework","version":3,"mbox":"http://patchwork.ozlabs.org/series/3652/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/814941/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/814941/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xwnPp2zmNz9s7M\n\tfor ;\n\tMon, 18 Sep 2017 23:47:42 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S932586AbdIRNq5 (ORCPT );\n\tMon, 18 Sep 2017 09:46:57 -0400","from michel.telenet-ops.be ([195.130.137.88]:47110 \"EHLO\n\tmichel.telenet-ops.be\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1755080AbdIRNqw (ORCPT\n\t); Mon, 18 Sep 2017 09:46:52 -0400","from ayla.of.borg ([84.195.106.246])\n\tby michel.telenet-ops.be with bizsmtp\n\tid B1mp1w0215JzmfG061mpbY; Mon, 18 Sep 2017 15:46:50 +0200","from ramsan.of.borg ([192.168.97.29] helo=ramsan)\n\tby ayla.of.borg with esmtp (Exim 4.86_2)\n\t(envelope-from )\n\tid 1dtwNp-0005uI-Or; Mon, 18 Sep 2017 15:46:45 +0200","from geert by ramsan with local (Exim 4.86_2)\n\t(envelope-from )\n\tid 1dtwNt-0008EG-Kn; Mon, 18 Sep 2017 15:46:49 +0200"],"From":"Geert Uytterhoeven ","To":"Daniel Lezcano ,\n\tThomas Gleixner , Rob Herring ,\n\tMark Rutland ,\n\tMagnus Damm ","Cc":"Laurent Pinchart ,\n\tdevicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org,\n\tGeert Uytterhoeven ","Subject":"[PATCH v3 1/7] dt-bindings: timer: renesas,\n\tcmt: Fix SoC-specific compatible values","Date":"Mon, 18 Sep 2017 15:46:41 +0200","Message-Id":"<1505742407-31576-2-git-send-email-geert+renesas@glider.be>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1505742407-31576-1-git-send-email-geert+renesas@glider.be>","References":"<1505742407-31576-1-git-send-email-geert+renesas@glider.be>","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"},"content":"While the new family-specific compatible values introduced by commit\n6f54cc1adcc8957f (\"devicetree: bindings: R-Car Gen2 CMT0 and CMT1\nbindings\") use the recommended order \",-\", the\nnew SoC-specific compatible values still use the old and deprecated\norder \",-\".\n\nSwitch the SoC-specific compatible values to the recommended order while\nthere are no upstream users of these compatible values yet.\n\nFixes: 7f03a0ecfdc786c1 (\"devicetree: bindings: r8a73a4 and R-Car Gen2 CMT bindings\")\nFixes: 63d9e8ca0dd4bfa4 (\"devicetree: bindings: Deprecate property, update example\")\nSigned-off-by: Geert Uytterhoeven \n---\nv3:\n - New.\n---\n .../devicetree/bindings/timer/renesas,cmt.txt | 24 +++++++++++-----------\n 1 file changed, 12 insertions(+), 12 deletions(-)","diff":"diff --git a/Documentation/devicetree/bindings/timer/renesas,cmt.txt b/Documentation/devicetree/bindings/timer/renesas,cmt.txt\nindex 6ca6b9e582a0e803..d740989eb56981cb 100644\n--- a/Documentation/devicetree/bindings/timer/renesas,cmt.txt\n+++ b/Documentation/devicetree/bindings/timer/renesas,cmt.txt\n@@ -20,16 +20,16 @@ Required Properties:\n \t\t(CMT1 on sh73a0 and r8a7740)\n \t\tThis is a fallback for the above renesas,cmt-48-* entries.\n \n- - \"renesas,cmt0-r8a73a4\" for the 32-bit CMT0 device included in r8a73a4.\n- - \"renesas,cmt1-r8a73a4\" for the 48-bit CMT1 device included in r8a73a4.\n- - \"renesas,cmt0-r8a7790\" for the 32-bit CMT0 device included in r8a7790.\n- - \"renesas,cmt1-r8a7790\" for the 48-bit CMT1 device included in r8a7790.\n- - \"renesas,cmt0-r8a7791\" for the 32-bit CMT0 device included in r8a7791.\n- - \"renesas,cmt1-r8a7791\" for the 48-bit CMT1 device included in r8a7791.\n- - \"renesas,cmt0-r8a7793\" for the 32-bit CMT0 device included in r8a7793.\n- - \"renesas,cmt1-r8a7793\" for the 48-bit CMT1 device included in r8a7793.\n- - \"renesas,cmt0-r8a7794\" for the 32-bit CMT0 device included in r8a7794.\n- - \"renesas,cmt1-r8a7794\" for the 48-bit CMT1 device included in r8a7794.\n+ - \"renesas,r8a73a4-cmt0\" for the 32-bit CMT0 device included in r8a73a4.\n+ - \"renesas,r8a73a4-cmt1\" for the 48-bit CMT1 device included in r8a73a4.\n+ - \"renesas,r8a7790-cmt0\" for the 32-bit CMT0 device included in r8a7790.\n+ - \"renesas,r8a7790-cmt1\" for the 48-bit CMT1 device included in r8a7790.\n+ - \"renesas,r8a7791-cmt0\" for the 32-bit CMT0 device included in r8a7791.\n+ - \"renesas,r8a7791-cmt1\" for the 48-bit CMT1 device included in r8a7791.\n+ - \"renesas,r8a7793-cmt0\" for the 32-bit CMT0 device included in r8a7793.\n+ - \"renesas,r8a7793-cmt1\" for the 48-bit CMT1 device included in r8a7793.\n+ - \"renesas,r8a7794-cmt0\" for the 32-bit CMT0 device included in r8a7794.\n+ - \"renesas,r8a7794-cmt1\" for the 48-bit CMT1 device included in r8a7794.\n \n - \"renesas,rcar-gen2-cmt0\" for 32-bit CMT0 devices included in R-Car Gen2.\n - \"renesas,rcar-gen2-cmt1\" for 48-bit CMT1 devices included in R-Car Gen2.\n@@ -46,7 +46,7 @@ Required Properties:\n Example: R8A7790 (R-Car H2) CMT0 and CMT1 nodes\n \n \tcmt0: timer@ffca0000 {\n-\t\tcompatible = \"renesas,cmt0-r8a7790\", \"renesas,rcar-gen2-cmt0\";\n+\t\tcompatible = \"renesas,r8a7790-cmt0\", \"renesas,rcar-gen2-cmt0\";\n \t\treg = <0 0xffca0000 0 0x1004>;\n \t\tinterrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,\n \t\t\t <0 142 IRQ_TYPE_LEVEL_HIGH>;\n@@ -55,7 +55,7 @@ Example: R8A7790 (R-Car H2) CMT0 and CMT1 nodes\n \t};\n \n \tcmt1: timer@e6130000 {\n-\t\tcompatible = \"renesas,cmt1-r8a7790\", \"renesas,rcar-gen2-cmt1\";\n+\t\tcompatible = \"renesas,r8a7790-cmt1\", \"renesas,rcar-gen2-cmt1\";\n \t\treg = <0 0xe6130000 0 0x1004>;\n \t\tinterrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,\n \t\t\t <0 121 IRQ_TYPE_LEVEL_HIGH>,\n","prefixes":["v3","1/7"]}