{"id":814940,"url":"http://patchwork.ozlabs.org/api/patches/814940/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-imx/patch/20170918134610.17743-3-jbrunet@baylibre.com/","project":{"id":19,"url":"http://patchwork.ozlabs.org/api/projects/19/?format=json","name":"Linux IMX development","link_name":"linux-imx","list_id":"linux-imx-kernel.lists.patchwork.ozlabs.org","list_email":"linux-imx-kernel@lists.patchwork.ozlabs.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170918134610.17743-3-jbrunet@baylibre.com>","list_archive_url":null,"date":"2017-09-18T13:46:09","name":"[v4,1/2] dt-bindings: interrupt-controller: add DT binding for meson GPIO interrupt controller","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"98422ce3c4ac6274e58a23a15596e70eb97e7662","submitter":{"id":69839,"url":"http://patchwork.ozlabs.org/api/people/69839/?format=json","name":"Jerome Brunet","email":"jbrunet@baylibre.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-imx/patch/20170918134610.17743-3-jbrunet@baylibre.com/mbox/","series":[{"id":3651,"url":"http://patchwork.ozlabs.org/api/series/3651/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-imx/list/?series=3651","date":"2017-09-18T13:46:07","name":"irqchip: meson: add support for the gpio interrupt controller","version":4,"mbox":"http://patchwork.ozlabs.org/series/3651/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/814940/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/814940/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-transfer-encoding;\n\tbh=r/zvGjiMzT2GM5av7cyQS7Gvu/XjANYw4OUvXWzraqM=;\n\tb=VZfzFF4Z7/r0SkluRKAZwTgHG0OWLUwgzaJfNmLYh3TWMiEWkfKVWKmTgW8zCt3bTL\n\tvqtpTkWTVQIu/vbk9S3OelpA0kzhOzlwPOrJyoR0Hk/DCsv8sFhqMWTyEf+MgwazvgcN\n\tDxGzRx528zovmYmqNJTGEjO6uFn8usqPCAg89MxBrpAqzXMFwESQxTaQvXAJQTgyp7Mk\n\ta7nFv4RKkXfxyINHNStyn+GdEB6tdFjYvigzrkaWOqAFhWz+OJ+/mPC0pspDOeCXmq3v\n\tOsaQWOT5qURluIvFwm/9bkarPBDC8VG+4gIO8K88CQ5sEEmn+Vv+Wl0hGaSqVfVeqh3H\n\tcxvg==","X-Gm-Message-State":"AHPjjUioihxRsh4KUEs/qh7AZGtTKP+FxmMMjflPYboK8HSbISB7ZUMN\n\tvMqCxVybW+vc9664EP0=","X-Google-Smtp-Source":"AOwi7QD7NhV5zDbzrJbhH/J0yNIThvodOAkN/cYBtvwszYIEe7VxbvR7gGNkAWtzwQ9mcAg/LuDHJQ==","X-Received":"by 10.223.161.137 with SMTP id u9mr14967752wru.280.1505742376200;\n\tMon, 18 Sep 2017 06:46:16 -0700 (PDT)","From":"Jerome Brunet ","To":"Marc Zyngier , Thomas Gleixner ,\n\tJason Cooper ,\n\tHeiner Kallweit ","Subject":"[PATCH v4 1/2] dt-bindings: interrupt-controller: add DT binding for\n\tmeson GPIO interrupt controller","Date":"Mon, 18 Sep 2017 15:46:09 +0200","Message-Id":"<20170918134610.17743-3-jbrunet@baylibre.com>","X-Mailer":"git-send-email 2.13.5","In-Reply-To":"<20170918134610.17743-1-jbrunet@baylibre.com>","References":"<20170918134610.17743-1-jbrunet@baylibre.com>","MIME-Version":"1.0","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170918_064638_220298_9BD8088F ","X-CRM114-Status":"GOOD ( 14.98 )","X-Spam-Score":"-1.2 (-)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-1.2 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/,\n\tno\n\ttrust [2a00:1450:400c:c0c:0:0:0:231 listed in] [list.dnswl.org]\n\t0.7 SPF_SOFTFAIL SPF: sender does not match SPF record (softfail)\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"devicetree@vger.kernel.org, Kevin Hilman ,\n\tlinux-kernel@vger.kernel.org, Carlo Caione ,\n\tlinux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, \n\tJerome Brunet ","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"},"content":"This commit adds the device tree bindings description for Amlogic's GPIO\ninterrupt controller available on the meson8b, gxbb and gxl SoC families\n\nCc: Heiner Kallweit \nSigned-off-by: Jerome Brunet \n---\n .../amlogic,meson-gpio-intc.txt | 35 ++++++++++++++++++++++\n 1 file changed, 35 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt","diff":"diff --git a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt\nnew file mode 100644\nindex 000000000000..633e21ce4b17\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt\n@@ -0,0 +1,35 @@\n+Amlogic meson GPIO interrupt controller\n+\n+Meson SoCs contains an interrupt controller which is able to watch the SoC\n+pads and generate an interrupt on edge or level. The controller is essentially\n+a 256 pads to 8 GIC interrupt multiplexer, with a filter block to select edge\n+or level and polarity. It does not expose all 256 mux inputs because the\n+documentation shows that the upper part is not mapped to any pad. The actual\n+number of interrupt exposed depends on the SoC.\n+\n+Required properties:\n+\n+- compatible : must have \"amlogic,meson8-gpio-intc” and either\n+ “amlogic,meson8b-gpio-intc” for meson8b SoCs (S805) or\n+ “amlogic,meson-gxbb-gpio-intc” for GXBB SoCs (S905) or\n+ “amlogic,meson-gxl-gpio-intc” for GXL SoCs (S905X, S912)\n+- interrupt-parent : a phandle to the GIC the interrupts are routed to.\n+ Usually this is provided at the root level of the device tree as it is\n+ common to most of the SoC.\n+- reg : Specifies base physical address and size of the registers.\n+- interrupt-controller : Identifies the node as an interrupt controller.\n+- #interrupt-cells : Specifies the number of cells needed to encode an\n+ interrupt source. The value must be 2.\n+- meson,channel-interrupts: Array with the 8 upstream hwirq numbers. These\n+ are the hwirqs used on the parent interrupt controller.\n+\n+Example:\n+\n+gpio_interrupt: interrupt-controller@9880 {\n+\tcompatible = \"amlogic,meson-gxbb-gpio-intc\",\n+\t\t \"amlogic,meson-gpio-intc\";\n+\treg = <0x0 0x9880 0x0 0x10>;\n+\tinterrupt-controller;\n+\t#interrupt-cells = <2>;\n+\tmeson,channel-interrupts = <64 65 66 67 68 69 70 71>;\n+};\n","prefixes":["v4","1/2"]}