{"id":814821,"url":"http://patchwork.ozlabs.org/api/patches/814821/?format=json","web_url":"http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20170918082706.6485-5-npiggin@gmail.com/","project":{"id":2,"url":"http://patchwork.ozlabs.org/api/projects/2/?format=json","name":"Linux PPC development","link_name":"linuxppc-dev","list_id":"linuxppc-dev.lists.ozlabs.org","list_email":"linuxppc-dev@lists.ozlabs.org","web_url":"https://github.com/linuxppc/wiki/wiki","scm_url":"https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git","webscm_url":"https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/","list_archive_url":"https://lore.kernel.org/linuxppc-dev/","list_archive_url_format":"https://lore.kernel.org/linuxppc-dev/{}/","commit_url_format":"https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}"},"msgid":"<20170918082706.6485-5-npiggin@gmail.com>","list_archive_url":"https://lore.kernel.org/linuxppc-dev/20170918082706.6485-5-npiggin@gmail.com/","date":"2017-09-18T08:27:05","name":"[4/5] powerpc/xmon: avoid tripping SMP hardlockup watchdog","commit_ref":null,"pull_url":null,"state":"superseded","archived":true,"hash":"9907e3a40bad5efc676978cc0a46654eb5ee7f6e","submitter":{"id":69518,"url":"http://patchwork.ozlabs.org/api/people/69518/?format=json","name":"Nicholas Piggin","email":"npiggin@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20170918082706.6485-5-npiggin@gmail.com/mbox/","series":[{"id":3584,"url":"http://patchwork.ozlabs.org/api/series/3584/?format=json","web_url":"http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=3584","date":"2017-09-18T08:27:01","name":"More NMI IPI enablement work","version":1,"mbox":"http://patchwork.ozlabs.org/series/3584/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/814821/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/814821/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xwfVb3pT6z9rxm\n\tfor ;\n\tMon, 18 Sep 2017 18:36:23 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xwfVb2gbmzDqGs\n\tfor ;\n\tMon, 18 Sep 2017 18:36:23 +1000 (AEST)","from mail-pf0-x244.google.com (mail-pf0-x244.google.com\n\t[IPv6:2607:f8b0:400e:c00::244])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xwfJN0J2LzDrWk\n\tfor ;\n\tMon, 18 Sep 2017 18:27:32 +1000 (AEST)","by mail-pf0-x244.google.com with SMTP id h4so4311992pfk.0\n\tfor ;\n\tMon, 18 Sep 2017 01:27:31 -0700 (PDT)","from roar.au.ibm.com ([210.185.119.235])\n\tby smtp.gmail.com with ESMTPSA id\n\td18sm14293750pfk.11.2017.09.18.01.27.27\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tMon, 18 Sep 2017 01:27:28 -0700 (PDT)"],"Authentication-Results":["ozlabs.org; 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a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=3qkX38bBdDtI1NNNQZ9YOle5nNrzchrgQ2Jn52j/VgI=;\n\tb=qRuNGz0c+OYwkkHOFP1zLldpfW5c9NQVr3oCUvGs605ku9bV1+9GkLSl07XkituHgl\n\t2Qbx6fL5iC4tDL6xoZor3i257b75jPZtoR6f7iqenOvumciu541i+qb4XsHl8hWHSBrn\n\tER0f1SJu5knqu3hiHF2mPV9RajMbeDa/1OtQENvP4tkZQrOPE+V9avm4WnWf7/Tr9eyi\n\th7Il4gGPDhAdQSDv6jw8T877KWRbXYqhMzkKYayiWOkrcYBDKAoXksu51sC0FGGbpd2c\n\tmFrcl3Ltv7FdAjHALP/SJhX0dr/xizspnxc08OlNZfK390weyNnt5SQTFBNflSybLS7a\n\tmuNQ==","X-Gm-Message-State":"AHPjjUgKXatHts42xU69NXnu7sTnXW6g2QIPXNnVSABCl0sqHB+jvekj\n\tigCrLc2kIXgycmAT","X-Google-Smtp-Source":"AOwi7QB6a9ychldKJYkTVwcEov14FZFEQ3IGzSivWJ0l+k0jkqbRnLnjvYgl658ZhFANhMHhLwtCKg==","X-Received":"by 10.84.235.65 with SMTP id g1mr19176813plt.353.1505723249824; \n\tMon, 18 Sep 2017 01:27:29 -0700 (PDT)","From":"Nicholas Piggin ","To":"linuxppc-dev@lists.ozlabs.org","Subject":"[PATCH 4/5] powerpc/xmon: avoid tripping SMP hardlockup watchdog","Date":"Mon, 18 Sep 2017 18:27:05 +1000","Message-Id":"<20170918082706.6485-5-npiggin@gmail.com>","X-Mailer":"git-send-email 2.13.3","In-Reply-To":"<20170918082706.6485-1-npiggin@gmail.com>","References":"<20170918082706.6485-1-npiggin@gmail.com>","X-BeenThere":"linuxppc-dev@lists.ozlabs.org","X-Mailman-Version":"2.1.24","Precedence":"list","List-Id":"Linux on PowerPC Developers Mail List\n\t","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Nicholas Piggin ","Errors-To":"linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org","Sender":"\"Linuxppc-dev\"\n\t"},"content":"The SMP hardlockup watchdog cross-checks other CPUs for lockups,\nwhich causes xmon headaches because it's assuming interrupts\nhard disabled means no watchdog troubles. Try to improve that by\ncalling touch_nmi_watchdog() in obvious places where secondaries\nare spinning.\n\nAlso annotate these spin loops with spin_begin/end calls.\n\nSigned-off-by: Nicholas Piggin \n---\n arch/powerpc/xmon/xmon.c | 17 +++++++++++++----\n 1 file changed, 13 insertions(+), 4 deletions(-)","diff":"diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c\nindex 33351c6704b1..d9a12102b111 100644\n--- a/arch/powerpc/xmon/xmon.c\n+++ b/arch/powerpc/xmon/xmon.c\n@@ -530,14 +530,19 @@ static int xmon_core(struct pt_regs *regs, int fromipi)\n \n waiting:\n \tsecondary = 1;\n+\tspin_begin();\n \twhile (secondary && !xmon_gate) {\n \t\tif (in_xmon == 0) {\n-\t\t\tif (fromipi)\n+\t\t\tif (fromipi) {\n+\t\t\t\tspin_end();\n \t\t\t\tgoto leave;\n+\t\t\t}\n \t\t\tsecondary = test_and_set_bit(0, &in_xmon);\n \t\t}\n-\t\tbarrier();\n+\t\tspin_cpu_relax();\n+\t\ttouch_nmi_watchdog();\n \t}\n+\tspin_end();\n \n \tif (!secondary && !xmon_gate) {\n \t\t/* we are the first cpu to come in */\n@@ -568,21 +573,25 @@ static int xmon_core(struct pt_regs *regs, int fromipi)\n \t\tmb();\n \t\txmon_gate = 1;\n \t\tbarrier();\n+\t\ttouch_nmi_watchdog();\n \t}\n \n cmdloop:\n \twhile (in_xmon) {\n \t\tif (secondary) {\n+\t\t\tspin_begin();\n \t\t\tif (cpu == xmon_owner) {\n \t\t\t\tif (!test_and_set_bit(0, &xmon_taken)) {\n \t\t\t\t\tsecondary = 0;\n+\t\t\t\t\tspin_end();\n \t\t\t\t\tcontinue;\n \t\t\t\t}\n \t\t\t\t/* missed it */\n \t\t\t\twhile (cpu == xmon_owner)\n-\t\t\t\t\tbarrier();\n+\t\t\t\t\tspin_cpu_relax();\n \t\t\t}\n-\t\t\tbarrier();\n+\t\t\tspin_cpu_relax();\n+\t\t\ttouch_nmi_watchdog();\n \t\t} else {\n \t\t\tcmd = cmds(regs);\n \t\t\tif (cmd != 0) {\n","prefixes":["4/5"]}