{"id":814663,"url":"http://patchwork.ozlabs.org/api/patches/814663/?format=json","web_url":"http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20170917164523.6970-2-martin.blumenstingl@googlemail.com/","project":{"id":37,"url":"http://patchwork.ozlabs.org/api/projects/37/?format=json","name":"Devicetree Bindings","link_name":"devicetree-bindings","list_id":"devicetree.vger.kernel.org","list_email":"devicetree@vger.kernel.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170917164523.6970-2-martin.blumenstingl@googlemail.com>","list_archive_url":null,"date":"2017-09-17T16:45:18","name":"[v7,1/6] dt-bindings: Amlogic: Add Meson8 and Meson8b SMP related documentation","commit_ref":null,"pull_url":null,"state":"not-applicable","archived":true,"hash":"5fed2989f5fcd2dff5f5c5b19234e9fbb8505bcf","submitter":{"id":66366,"url":"http://patchwork.ozlabs.org/api/people/66366/?format=json","name":"Martin Blumenstingl","email":"martin.blumenstingl@googlemail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20170917164523.6970-2-martin.blumenstingl@googlemail.com/mbox/","series":[{"id":3524,"url":"http://patchwork.ozlabs.org/api/series/3524/?format=json","web_url":"http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=3524","date":"2017-09-17T16:45:17","name":"SMP and CPU hotplug support for Meson8/Meson8b","version":7,"mbox":"http://patchwork.ozlabs.org/series/3524/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/814663/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/814663/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; 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s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=yNofJgu54TNPKYLLLiHOX3wDRD771jQcVEM3pet/8CM=;\n\tb=j1FWUtIZ+N6HIaQeD8pqlB8oxNeHf7mRxKnYFsYOqMnVPX0j+4NUqud08YcrTS6yso\n\tWCNF6nzt3KUD+qGZuYLxU/WWguLnLtXY3MvZ6kZ7Ebtr0WaqvIapzRa5GYLgAw7tt1D1\n\tFa6TEy31MsVwyTq7R+1CMWi9Pk/6NNkd1b8oaANvpj/n9IUgyfg6UCeaMxyKeXPQjxgd\n\tjG9Y0GeY7pobEj1ouxRCOQUxWQnbpPBCRPodZN8x0aebeK64SWI8gYCKQCI7CiMKwKZk\n\tTW0LppjkNorEC6gj92bDT03VxSNE4UdsjZ3wZzVAnArRemLR00m7+HLrZrTJiSL7FsZo\n\tjCLw==","X-Gm-Message-State":"AHPjjUjfKATYmgwhgSoZGjXM1R790qsxIrNAi+6/WwOKhtfeqLEhV6rP\n\ty89yG72NNWfd8A==","X-Google-Smtp-Source":"AOwi7QB5DqForYmselpIpcwvFBuCtzeHa1S49P2Oxcj9svNXjLKg0hugpDv/k1UzOeHb5B0PM4LBVQ==","X-Received":"by 10.28.11.195 with SMTP id 186mr6592789wml.41.1505666751014;\n\tSun, 17 Sep 2017 09:45:51 -0700 (PDT)","From":"Martin Blumenstingl ","To":"linux-amlogic@lists.infradead.org,\n\tlinux-arm-kernel@lists.infradead.org, khilman@baylibre.com,\n\tcarlo@caione.org, linux@armlinux.org.uk","Cc":"robh+dt@kernel.org, devicetree@vger.kernel.org, arnd@arndb.de,\n\tmark.rutland@arm.com, f.fainelli@gmail.com,\n\tCarlo Caione ,\n\tMartin Blumenstingl ","Subject":"[PATCH v7 1/6] dt-bindings: Amlogic: Add Meson8 and Meson8b SMP\n\trelated documentation","Date":"Sun, 17 Sep 2017 18:45:18 +0200","Message-Id":"<20170917164523.6970-2-martin.blumenstingl@googlemail.com>","X-Mailer":"git-send-email 2.14.1","In-Reply-To":"<20170917164523.6970-1-martin.blumenstingl@googlemail.com>","References":"<20170917164523.6970-1-martin.blumenstingl@googlemail.com>","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"},"content":"From: Carlo Caione \n\nWith this patch we add documentation for:\n\n* power-management-unit: the PMU is used to bring up the cores during\n SMP operations\n* sram: among other things the sram is used to store the first code\n executed by the core when it is powered up\n* cpu-enable-method: the CPU enable method used by Amlogic Meson8 and\n Meson8b SoCs\n\nSigned-off-by: Carlo Caione \n[also add Meson8 to the documentation]\nSigned-off-by: Martin Blumenstingl \nAcked-by: Rob Herring \n---\n .../devicetree/bindings/arm/amlogic/pmu.txt | 18 ++++++++++++\n .../devicetree/bindings/arm/amlogic/smp-sram.txt | 32 ++++++++++++++++++++++\n Documentation/devicetree/bindings/arm/cpus.txt | 2 ++\n 3 files changed, 52 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/arm/amlogic/pmu.txt\n create mode 100644 Documentation/devicetree/bindings/arm/amlogic/smp-sram.txt","diff":"diff --git a/Documentation/devicetree/bindings/arm/amlogic/pmu.txt b/Documentation/devicetree/bindings/arm/amlogic/pmu.txt\nnew file mode 100644\nindex 000000000000..72f8d08198b6\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/arm/amlogic/pmu.txt\n@@ -0,0 +1,18 @@\n+Amlogic Meson8 and Meson8b power-management-unit:\n+-------------------------------------------------\n+\n+The pmu is used to turn off and on different power domains of the SoCs\n+This includes the power to the CPU cores.\n+\n+Required node properties:\n+- compatible value : depending on the SoC this should be one of:\n+\t\t\t\"amlogic,meson8-pmu\"\n+\t\t\t\"amlogic,meson8b-pmu\"\n+- reg : physical base address and the size of the registers window\n+\n+Example:\n+\n+\tpmu@c81000e4 {\n+\t\tcompatible = \"amlogic,meson8b-pmu\", \"syscon\";\n+\t\treg = <0xc81000e0 0x18>;\n+\t};\ndiff --git a/Documentation/devicetree/bindings/arm/amlogic/smp-sram.txt b/Documentation/devicetree/bindings/arm/amlogic/smp-sram.txt\nnew file mode 100644\nindex 000000000000..3473ddaadfac\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/arm/amlogic/smp-sram.txt\n@@ -0,0 +1,32 @@\n+Amlogic Meson8 and Meson8b SRAM for smp bringup:\n+------------------------------------------------\n+\n+Amlogic's SMP-capable SoCs use part of the sram for the bringup of the cores.\n+Once the core gets powered up it executes the code that is residing at a\n+specific location.\n+\n+Therefore a reserved section sub-node has to be added to the mmio-sram\n+declaration.\n+\n+Required sub-node properties:\n+- compatible : depending on the SoC this should be one of:\n+\t\t\"amlogic,meson8-smp-sram\"\n+\t\t\"amlogic,meson8b-smp-sram\"\n+\n+The rest of the properties should follow the generic mmio-sram discription\n+found in ../../misc/sram.txt\n+\n+Example:\n+\n+\tsram: sram@d9000000 {\n+\t\tcompatible = \"mmio-sram\";\n+\t\treg = <0xd9000000 0x20000>;\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\tranges = <0 0xd9000000 0x20000>;\n+\n+\t\tsmp-sram@1ff80 {\n+\t\t\tcompatible = \"amlogic,meson8b-smp-sram\";\n+\t\t\treg = <0x1ff80 0x8>;\n+\t\t};\n+\t};\ndiff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt\nindex b92f12bd5244..a0009b72e9be 100644\n--- a/Documentation/devicetree/bindings/arm/cpus.txt\n+++ b/Documentation/devicetree/bindings/arm/cpus.txt\n@@ -197,6 +197,8 @@ described below.\n \t\t\t \"actions,s500-smp\"\n \t\t\t \"allwinner,sun6i-a31\"\n \t\t\t \"allwinner,sun8i-a23\"\n+\t\t\t \"amlogic,meson8-smp\"\n+\t\t\t \"amlogic,meson8b-smp\"\n \t\t\t \"arm,realview-smp\"\n \t\t\t \"brcm,bcm11351-cpu-method\"\n \t\t\t \"brcm,bcm23550\"\n","prefixes":["v7","1/6"]}