{"id":814509,"url":"http://patchwork.ozlabs.org/api/patches/814509/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/e2316c11d48279f3fff70ffc28d44854ace1d716.1505570561.git.balaton@eik.bme.hu/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"","list_archive_url":null,"date":"2017-09-16T14:02:41","name":"[v2,3/4] ppc4xx: Add more PLB registers","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"8b9d7afc1f95751b66a33b533b05d6062208f6a0","submitter":{"id":16148,"url":"http://patchwork.ozlabs.org/api/people/16148/?format=json","name":"BALATON Zoltan","email":"balaton@eik.bme.hu"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/e2316c11d48279f3fff70ffc28d44854ace1d716.1505570561.git.balaton@eik.bme.hu/mbox/","series":[{"id":3444,"url":"http://patchwork.ozlabs.org/api/series/3444/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=3444","date":"2017-09-16T14:02:41","name":"Sam460ex emulation","version":2,"mbox":"http://patchwork.ozlabs.org/series/3444/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/814509/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/814509/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xvYzr17FXz9t2M\n\tfor ;\n\tSun, 17 Sep 2017 00:09:28 +1000 (AEST)","from localhost ([::1]:57429 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dtDmg-0006iD-6C\n\tfor incoming@patchwork.ozlabs.org; Sat, 16 Sep 2017 10:09:26 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:42168)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1dtDlp-0006fY-Rf\n\tfor qemu-devel@nongnu.org; Sat, 16 Sep 2017 10:08:34 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1dtDln-0003TM-Pq\n\tfor qemu-devel@nongnu.org; Sat, 16 Sep 2017 10:08:33 -0400","from zero.eik.bme.hu ([2001:738:2001:2001::2001]:41146)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from ) id 1dtDln-0003Sl-Ia\n\tfor qemu-devel@nongnu.org; Sat, 16 Sep 2017 10:08:31 -0400","from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182])\n\tby localhost (Postfix) with SMTP id 9F6917456F6;\n\tSat, 16 Sep 2017 16:08:16 +0200 (CEST)","by zero.eik.bme.hu (Postfix, from userid 432)\n\tid ED3C57456EF; Sat, 16 Sep 2017 16:08:15 +0200 (CEST)"],"Message-Id":"","In-Reply-To":"","References":"","From":"BALATON Zoltan ","Date":"Sat, 16 Sep 2017 16:02:41 +0200","To":"qemu-devel@nongnu.org,\n qemu-ppc@nongnu.org","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2001:738:2001:2001::2001","Subject":"[Qemu-devel] [PATCH v2 3/4] ppc4xx: Add more PLB registers","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Francois Revol , Alexander Graf ,\n\tDavid Gibson ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"These registers are present in 440 SoCs (and maybe in others too) and\nU-Boot accesses them when printing register info. We don't emulate\nthese but add them to avoid crashing when they are read or written.\n\nSigned-off-by: BALATON Zoltan \n---\nv2: No change, discussed in: http://lists.nongnu.org/archive/html/qemu-ppc/2017-08/msg00385.html\n\n hw/ppc/ppc405_uc.c | 12 +++++++++---\n 1 file changed, 9 insertions(+), 3 deletions(-)","diff":"diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c\nindex e621d0a..8e58065 100644\n--- a/hw/ppc/ppc405_uc.c\n+++ b/hw/ppc/ppc405_uc.c\n@@ -105,9 +105,12 @@ ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,\n /*****************************************************************************/\n /* Peripheral local bus arbitrer */\n enum {\n- PLB0_BESR = 0x084,\n- PLB0_BEAR = 0x086,\n- PLB0_ACR = 0x087,\n+ PLB3A0_ACR = 0x077,\n+ PLB4A0_ACR = 0x081,\n+ PLB0_BESR = 0x084,\n+ PLB0_BEAR = 0x086,\n+ PLB0_ACR = 0x087,\n+ PLB4A1_ACR = 0x089,\n };\n \n typedef struct ppc4xx_plb_t ppc4xx_plb_t;\n@@ -179,9 +182,12 @@ void ppc4xx_plb_init(CPUPPCState *env)\n ppc4xx_plb_t *plb;\n \n plb = g_malloc0(sizeof(ppc4xx_plb_t));\n+ ppc_dcr_register(env, PLB3A0_ACR, plb, &dcr_read_plb, &dcr_write_plb);\n+ ppc_dcr_register(env, PLB4A0_ACR, plb, &dcr_read_plb, &dcr_write_plb);\n ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);\n ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);\n ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);\n+ ppc_dcr_register(env, PLB4A1_ACR, plb, &dcr_read_plb, &dcr_write_plb);\n qemu_register_reset(ppc4xx_plb_reset, plb);\n }\n \n","prefixes":["v2","3/4"]}