{"id":814508,"url":"http://patchwork.ozlabs.org/api/patches/814508/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/feadb6b3124f9d921754b54621257bf002935551.1505570561.git.balaton@eik.bme.hu/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"","list_archive_url":null,"date":"2017-09-16T14:02:41","name":"[v2,4/4] ppc: Add 460EX embedded CPU","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"95304156ce5a7893767f4c92418dd722774c0310","submitter":{"id":16148,"url":"http://patchwork.ozlabs.org/api/people/16148/?format=json","name":"BALATON Zoltan","email":"balaton@eik.bme.hu"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/feadb6b3124f9d921754b54621257bf002935551.1505570561.git.balaton@eik.bme.hu/mbox/","series":[{"id":3444,"url":"http://patchwork.ozlabs.org/api/series/3444/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=3444","date":"2017-09-16T14:02:41","name":"Sam460ex emulation","version":2,"mbox":"http://patchwork.ozlabs.org/series/3444/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/814508/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/814508/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xvYzq3Y2dz9sPk\n\tfor ;\n\tSun, 17 Sep 2017 00:09:27 +1000 (AEST)","from localhost ([::1]:57430 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dtDmf-0006im-GH\n\tfor incoming@patchwork.ozlabs.org; Sat, 16 Sep 2017 10:09:25 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:42169)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1dtDlp-0006fZ-RX\n\tfor qemu-devel@nongnu.org; Sat, 16 Sep 2017 10:08:35 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1dtDlo-0003Ts-1W\n\tfor qemu-devel@nongnu.org; Sat, 16 Sep 2017 10:08:33 -0400","from zero.eik.bme.hu ([2001:738:2001:2001::2001]:41148)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from ) id 1dtDln-0003Sr-Me\n\tfor qemu-devel@nongnu.org; Sat, 16 Sep 2017 10:08:31 -0400","from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182])\n\tby localhost (Postfix) with SMTP id 6C2C274581D;\n\tSat, 16 Sep 2017 16:08:16 +0200 (CEST)","by zero.eik.bme.hu (Postfix, from userid 432)\n\tid EFB46745798; Sat, 16 Sep 2017 16:08:15 +0200 (CEST)"],"Message-Id":"","In-Reply-To":"","References":"","From":"BALATON Zoltan ","Date":"Sat, 16 Sep 2017 16:02:41 +0200","To":"qemu-devel@nongnu.org,\n qemu-ppc@nongnu.org","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2001:738:2001:2001::2001","Subject":"[Qemu-devel] [PATCH v2 4/4] ppc: Add 460EX embedded CPU","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Francois Revol , Alexander Graf ,\n\tDavid Gibson ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"Despite its name it is a 440 core CPU\n\nSigned-off-by: BALATON Zoltan \nReviewed-by: David Gibson \n---\nv2: Rebased to latest changes on master\n\n target/ppc/cpu-models.c | 3 +++\n target/ppc/cpu-models.h | 1 +\n target/ppc/translate_init.c | 38 ++++++++++++++++++++++++++++++++++++++\n 3 files changed, 42 insertions(+)","diff":"diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c\nindex 9626d6b..9d45702 100644\n--- a/target/ppc/cpu-models.c\n+++ b/target/ppc/cpu-models.c\n@@ -167,6 +167,8 @@\n \"PowerPC 440 EPb\")\n POWERPC_DEF(\"440epx\", CPU_POWERPC_440EPX, 440EP,\n \"PowerPC 440 EPX\")\n+ POWERPC_DEF(\"460exb\", CPU_POWERPC_460EXb, 460EX,\n+ \"PowerPC 460 EXb\")\n #if defined(TODO_USER_ONLY)\n POWERPC_DEF(\"440gpb\", CPU_POWERPC_440GPb, 440GP,\n \"PowerPC 440 GPb\")\n@@ -786,6 +788,7 @@ PowerPCCPUAlias ppc_cpu_aliases[] = {\n { \"x2vp50\", \"x2vp20\" },\n \n { \"440ep\", \"440epb\" },\n+ { \"460ex\", \"460exb\" },\n #if defined(TODO_USER_ONLY)\n { \"440gp\", \"440gpc\" },\n { \"440gr\", \"440gra\" },\ndiff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h\nindex df31d7f..ed64005 100644\n--- a/target/ppc/cpu-models.h\n+++ b/target/ppc/cpu-models.h\n@@ -240,6 +240,7 @@ enum {\n CPU_POWERPC_440SP = 0x53221850,\n CPU_POWERPC_440SP2 = 0x53221891,\n CPU_POWERPC_440SPE = 0x53421890,\n+ CPU_POWERPC_460EXb = 0x130218A4, /* called 460 but 440 core */\n /* PowerPC 460 family */\n #if 0\n /* Generic PowerPC 464 */\ndiff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c\nindex c827d1e..f36decd 100644\n--- a/target/ppc/translate_init.c\n+++ b/target/ppc/translate_init.c\n@@ -3833,6 +3833,44 @@ POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)\n POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;\n }\n \n+POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data)\n+{\n+ DeviceClass *dc = DEVICE_CLASS(oc);\n+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);\n+\n+ dc->desc = \"PowerPC 460 EX\";\n+ pcc->init_proc = init_proc_440EP;\n+ pcc->check_pow = check_pow_nocheck;\n+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |\n+ PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |\n+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |\n+ PPC_FLOAT_STFIWX |\n+ PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI |\n+ PPC_CACHE | PPC_CACHE_ICBI |\n+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA |\n+ PPC_MEM_TLBSYNC | PPC_MFTB |\n+ PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |\n+ PPC_440_SPEC;\n+ pcc->msr_mask = (1ull << MSR_POW) |\n+ (1ull << MSR_CE) |\n+ (1ull << MSR_EE) |\n+ (1ull << MSR_PR) |\n+ (1ull << MSR_FP) |\n+ (1ull << MSR_ME) |\n+ (1ull << MSR_FE0) |\n+ (1ull << MSR_DWE) |\n+ (1ull << MSR_DE) |\n+ (1ull << MSR_FE1) |\n+ (1ull << MSR_IR) |\n+ (1ull << MSR_DR);\n+ pcc->mmu_model = POWERPC_MMU_BOOKE;\n+ pcc->excp_model = POWERPC_EXCP_BOOKE;\n+ pcc->bus_model = PPC_FLAGS_INPUT_BookE;\n+ pcc->bfd_mach = bfd_mach_ppc_403;\n+ pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |\n+ POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;\n+}\n+\n static void init_proc_440GP(CPUPPCState *env)\n {\n /* Time base */\n","prefixes":["v2","4/4"]}