{"id":814364,"url":"http://patchwork.ozlabs.org/api/patches/814364/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20170915191029.28284-1-marek.vasut+renesas@gmail.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170915191029.28284-1-marek.vasut+renesas@gmail.com>","list_archive_url":null,"date":"2017-09-15T19:10:29","name":"[U-Boot] clk: rmobile: Add RPC hyperflash clock","commit_ref":"849ab0a66f1a1272022bab912bcbcc4e22648c66","pull_url":null,"state":"accepted","archived":false,"hash":"252ef67006094c5b8fdd239569ca438147813b5d","submitter":{"id":1124,"url":"http://patchwork.ozlabs.org/api/people/1124/?format=json","name":"Marek Vasut","email":"marek.vasut@gmail.com"},"delegate":{"id":1750,"url":"http://patchwork.ozlabs.org/api/users/1750/?format=json","username":"iwamatsu","first_name":"Nobuhiro","last_name":"Iwamatsu","email":"iwamatsu@nigauri.org"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20170915191029.28284-1-marek.vasut+renesas@gmail.com/mbox/","series":[{"id":3358,"url":"http://patchwork.ozlabs.org/api/series/3358/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=3358","date":"2017-09-15T19:10:29","name":"[U-Boot] clk: rmobile: Add RPC hyperflash clock","version":1,"mbox":"http://patchwork.ozlabs.org/series/3358/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/814364/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/814364/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"ugw9Mdfr\"; dkim-atps=neutral"],"Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xv4kb3vprz9s7g\n\tfor ;\n\tSat, 16 Sep 2017 05:11:17 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 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s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id;\n\tbh=QO5sbXLV3dkihJpzujV0SL6HSDdOK4tkbKxdLtVcVdM=;\n\tb=GMpLpVWyl6PS3RJa18pWxc7ILI+vk5X5V+o9ekyGtd8eJBWNhDMChgMa5yGDZYGbRu\n\tK8IP6UYjARBQLxDUaziobxAOqttodHpIb3yyC7u1Nr1mfLttJkNIFL5ts2kxAzTvGmQP\n\tO0XAh9c3qjiazmWRunG/s0DLTpeZJXjHzSWYdJp1TbCE38RQK9DqvieoSv6lG5pInpdr\n\tVUW7AxhGd48PTEWsjyO0VGDs9D4Uk0SpTWZgipUGnWhfJX86lZrd1pI9x0PWVo/twLWX\n\tSPgRjnW7+xxGksdxzflIcGN4yaHk9WH28QQ1cXr6JFx/kVX4LY6OsSeghXshKnWMDsY9\n\t+umQ==","X-Gm-Message-State":"AHPjjUh5Kq9cbo6JDDnian8J1LKcS82heh0qBihMCyC+4dsBGM4kgzlZ\n\tmBRtgMQRa/NQP5EBzlo=","X-Google-Smtp-Source":"AOwi7QABoKkY1G2YnG0CefaJ/+CI3kQOP1VrIDgBqBBdtCVysi9bg3gW3XFTFyOGWJ4tGoxH5Ef+Yw==","X-Received":"by 10.28.73.134 with SMTP id w128mr3389489wma.141.1505502634539; \n\tFri, 15 Sep 2017 12:10:34 -0700 (PDT)","From":"Marek Vasut ","X-Google-Original-From":"Marek Vasut ","To":"u-boot@lists.denx.de","Date":"Fri, 15 Sep 2017 21:10:29 +0200","Message-Id":"<20170915191029.28284-1-marek.vasut+renesas@gmail.com>","X-Mailer":"git-send-email 2.11.0","Cc":"Marek Vasut ","Subject":"[U-Boot] [PATCH] clk: rmobile: Add RPC hyperflash clock","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"Add missing RPC hyperflash entry into the clock driver tables.\n\nSigned-off-by: Marek Vasut \nCc: Nobuhiro Iwamatsu \n---\n drivers/clk/renesas/clk-rcar-gen3.c | 44 ++++++++++++++++++++++++++++++++++++-\n 1 file changed, 43 insertions(+), 1 deletion(-)","diff":"diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c\nindex 3326b61f3a..c821bddc25 100644\n--- a/drivers/clk/renesas/clk-rcar-gen3.c\n+++ b/drivers/clk/renesas/clk-rcar-gen3.c\n@@ -27,6 +27,11 @@\n #define CPG_PLL2CR\t\t0x002c\n #define CPG_PLL4CR\t\t0x01f4\n \n+#define CPG_RPC_PREDIV_MASK\t0x3\n+#define CPG_RPC_PREDIV_OFFSET\t3\n+#define CPG_RPC_POSTDIV_MASK\t0x7\n+#define CPG_RPC_POSTDIV_OFFSET\t0\n+\n /*\n * Module Standby and Software Reset register offets.\n *\n@@ -119,6 +124,8 @@ enum clk_types {\n \tDEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)\n #define DEF_GEN3_SD(_name, _id, _parent, _offset)\t\\\n \tDEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)\n+#define DEF_GEN3_RPC(_name, _id, _parent, _offset)\t\\\n+\tDEF_BASE(_name, _id, CLK_TYPE_GEN3_RPC, _parent, .offset = _offset)\n \n /*\n * Definitions of Module Clocks\n@@ -145,6 +152,7 @@ enum rcar_gen3_clk_types {\n \tCLK_TYPE_GEN3_PLL3,\n \tCLK_TYPE_GEN3_PLL4,\n \tCLK_TYPE_GEN3_SD,\n+\tCLK_TYPE_GEN3_RPC,\n \tCLK_TYPE_GEN3_R,\n };\n \n@@ -176,6 +184,7 @@ enum clk_ids {\n \tCLK_S2,\n \tCLK_S3,\n \tCLK_SDSRC,\n+\tCLK_RPCSRC,\n \tCLK_SSPSRC,\n \tCLK_RINT,\n \n@@ -203,6 +212,7 @@ static const struct cpg_core_clk r8a7795_core_clks[] = {\n \tDEF_FIXED(\".s2\", CLK_S2, CLK_PLL1_DIV2, 4, 1),\n \tDEF_FIXED(\".s3\", CLK_S3, CLK_PLL1_DIV2, 6, 1),\n \tDEF_FIXED(\".sdsrc\", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),\n+\tDEF_FIXED(\".rpcsrc\", CLK_RPCSRC, CLK_PLL1, 2, 1),\n \n \t/* Core Clock Outputs */\n \tDEF_FIXED(\"ztr\", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),\n@@ -231,6 +241,8 @@ static const struct cpg_core_clk r8a7795_core_clks[] = {\n \tDEF_GEN3_SD(\"sd2\", R8A7795_CLK_SD2, CLK_SDSRC, 0x268),\n \tDEF_GEN3_SD(\"sd3\", R8A7795_CLK_SD3, CLK_SDSRC, 0x26c),\n \n+\tDEF_GEN3_RPC(\"rpc\", R8A7795_CLK_RPC, CLK_RPCSRC, 0x238),\n+\n \tDEF_FIXED(\"cl\", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1),\n \tDEF_FIXED(\"cp\", R8A7795_CLK_CP, CLK_EXTAL, 2, 1),\n \n@@ -358,6 +370,7 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] = {\n \tDEF_MOD(\"can-fd\",\t\t 914,\tR8A7795_CLK_S3D2),\n \tDEF_MOD(\"can-if1\",\t\t 915,\tR8A7795_CLK_S3D4),\n \tDEF_MOD(\"can-if0\",\t\t 916,\tR8A7795_CLK_S3D4),\n+\tDEF_MOD(\"rpc\",\t\t\t 917,\tR8A7795_CLK_RPC),\n \tDEF_MOD(\"i2c6\",\t\t\t 918,\tR8A7795_CLK_S0D6),\n \tDEF_MOD(\"i2c5\",\t\t\t 919,\tR8A7795_CLK_S0D6),\n \tDEF_MOD(\"i2c-dvfs\",\t\t 926,\tR8A7795_CLK_CP),\n@@ -414,6 +427,7 @@ static const struct cpg_core_clk r8a7796_core_clks[] = {\n \tDEF_FIXED(\".s2\", CLK_S2, CLK_PLL1_DIV2, 4, 1),\n \tDEF_FIXED(\".s3\", CLK_S3, CLK_PLL1_DIV2, 6, 1),\n \tDEF_FIXED(\".sdsrc\", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),\n+\tDEF_FIXED(\".rpcsrc\", CLK_RPCSRC, CLK_PLL1, 2, 1),\n \n \t/* Core Clock Outputs */\n \tDEF_FIXED(\"ztr\", R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),\n@@ -442,6 +456,8 @@ static const struct cpg_core_clk r8a7796_core_clks[] = {\n \tDEF_GEN3_SD(\"sd2\", R8A7796_CLK_SD2, CLK_SDSRC, 0x268),\n \tDEF_GEN3_SD(\"sd3\", R8A7796_CLK_SD3, CLK_SDSRC, 0x26c),\n \n+\tDEF_GEN3_RPC(\"rpc\", R8A7796_CLK_RPC, CLK_RPCSRC, 0x238),\n+\n \tDEF_FIXED(\"cl\", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1),\n \tDEF_FIXED(\"cp\", R8A7796_CLK_CP, CLK_EXTAL, 2, 1),\n \n@@ -541,6 +557,7 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] = {\n \tDEF_MOD(\"can-fd\",\t\t 914,\tR8A7796_CLK_S3D2),\n \tDEF_MOD(\"can-if1\",\t\t 915,\tR8A7796_CLK_S3D4),\n \tDEF_MOD(\"can-if0\",\t\t 916,\tR8A7796_CLK_S3D4),\n+\tDEF_MOD(\"rpc\",\t\t\t 917,\tR8A7795_CLK_RPC),\n \tDEF_MOD(\"i2c6\",\t\t\t 918,\tR8A7796_CLK_S0D6),\n \tDEF_MOD(\"i2c5\",\t\t\t 919,\tR8A7796_CLK_S0D6),\n \tDEF_MOD(\"i2c-dvfs\",\t\t 926,\tR8A7796_CLK_CP),\n@@ -827,7 +844,7 @@ static ulong gen3_clk_get_rate(struct clk *clk)\n \tconst struct cpg_core_clk *core;\n \tconst struct rcar_gen3_cpg_pll_config *pll_config =\n \t\t\t\t\tpriv->cpg_pll_config;\n-\tu32 value, mult, rate = 0;\n+\tu32 value, mult, prediv, postdiv, rate = 0;\n \tint i, ret;\n \n \tdebug(\"%s[%i] Clock: id=%lu\\n\", __func__, __LINE__, clk->id);\n@@ -937,6 +954,31 @@ static ulong gen3_clk_get_rate(struct clk *clk)\n \t\t}\n \n \t\treturn -EINVAL;\n+\n+\tcase CLK_TYPE_GEN3_RPC:\n+\t\trate = gen3_clk_get_rate(&parent);\n+\n+\t\tvalue = readl(priv->base + core->offset);\n+\n+\t\tprediv = (value >> CPG_RPC_PREDIV_OFFSET) &\n+\t\t\t CPG_RPC_PREDIV_MASK;\n+\t\tif (prediv == 2)\n+\t\t\trate /= 5;\n+\t\telse if (prediv == 3)\n+\t\t\trate /= 6;\n+\t\telse\n+\t\t\treturn -EINVAL;\n+\n+\t\tpostdiv = (value >> CPG_RPC_POSTDIV_OFFSET) &\n+\t\t\t CPG_RPC_POSTDIV_MASK;\n+\t\trate /= postdiv + 1;\n+\n+\t\tdebug(\"%s[%i] RPC clk: parent=%i prediv=%i postdiv=%i => rate=%u\\n\",\n+\t\t __func__, __LINE__,\n+\t\t core->parent, prediv, postdiv, rate);\n+\n+\t\treturn -EINVAL;\n+\n \t}\n \n \tprintf(\"%s[%i] unknown fail\\n\", __func__, __LINE__);\n","prefixes":["U-Boot"]}