{"id":814360,"url":"http://patchwork.ozlabs.org/api/patches/814360/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170915190748.82389-1-jrtc27@jrtc27.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170915190748.82389-1-jrtc27@jrtc27.com>","list_archive_url":null,"date":"2017-09-15T19:07:48","name":"[v2] linux-user/syscall.c: Handle SH4's exceptional alignment for p{read, write}64","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"ace964710d0311b93169b0b481984d71c581bf7f","submitter":{"id":64682,"url":"http://patchwork.ozlabs.org/api/people/64682/?format=json","name":"Jessica Clarke","email":"jrtc27@jrtc27.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170915190748.82389-1-jrtc27@jrtc27.com/mbox/","series":[{"id":3354,"url":"http://patchwork.ozlabs.org/api/series/3354/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=3354","date":"2017-09-15T19:07:48","name":"[v2] linux-user/syscall.c: Handle SH4's exceptional alignment for p{read, write}64","version":2,"mbox":"http://patchwork.ozlabs.org/series/3354/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/814360/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/814360/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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}\n+static inline int regpairs_aligned(void *cpu_env, int num) { return 1; }\n #elif defined(TARGET_PPC) && !defined(TARGET_PPC64)\n /* SysV AVI for PPC32 expects 64bit parameters to be passed on odd/even pairs\n * of registers which translates to the same as ARM/MIPS, because we start with\n * r3 as arg1 */\n-static inline int regpairs_aligned(void *cpu_env) { return 1; }\n+static inline int regpairs_aligned(void *cpu_env, int num) { return 1; }\n+#elif defined(TARGET_SH4)\n+/* SH4 doesn't align register pairs, except for p{read,write}64 */\n+static inline int regpairs_aligned(void *cpu_env, int num) {\n+ switch (num) {\n+ case TARGET_NR_pread64:\n+ case TARGET_NR_pwrite64:\n+ return 1;\n+\n+ default:\n+ return 0;\n+ }\n+}\n #else\n-static inline int regpairs_aligned(void *cpu_env) { return 0; }\n+static inline int regpairs_aligned(void *cpu_env, int num) { return 0; }\n #endif\n \n #define ERRNO_TABLE_SIZE 1200\n@@ -6857,7 +6869,7 @@ static inline abi_long target_truncate64(void *cpu_env, const char *arg1,\n abi_long arg3,\n abi_long arg4)\n {\n- if (regpairs_aligned(cpu_env)) {\n+ if (regpairs_aligned(cpu_env, TARGET_NR_truncate64)) {\n arg2 = arg3;\n arg3 = arg4;\n }\n@@ -6871,7 +6883,7 @@ static inline abi_long target_ftruncate64(void *cpu_env, abi_long arg1,\n abi_long arg3,\n abi_long arg4)\n {\n- if (regpairs_aligned(cpu_env)) {\n+ if (regpairs_aligned(cpu_env, TARGET_NR_ftruncate64)) {\n arg2 = arg3;\n arg3 = arg4;\n }\n@@ -10495,7 +10507,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,\n #endif\n #ifdef TARGET_NR_pread64\n case TARGET_NR_pread64:\n- if (regpairs_aligned(cpu_env)) {\n+ if (regpairs_aligned(cpu_env, num)) {\n arg4 = arg5;\n arg5 = arg6;\n }\n@@ -10505,7 +10517,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,\n unlock_user(p, arg2, ret);\n break;\n case TARGET_NR_pwrite64:\n- if (regpairs_aligned(cpu_env)) {\n+ if (regpairs_aligned(cpu_env, num)) {\n arg4 = arg5;\n arg5 = arg6;\n }\n@@ -11275,7 +11287,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,\n arg6 = ret;\n #else\n /* 6 args: fd, offset (high, low), len (high, low), advice */\n- if (regpairs_aligned(cpu_env)) {\n+ if (regpairs_aligned(cpu_env, num)) {\n /* offset is in (3,4), len in (5,6) and advice in 7 */\n arg2 = arg3;\n arg3 = arg4;\n@@ -11294,7 +11306,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,\n #ifdef TARGET_NR_fadvise64\n case TARGET_NR_fadvise64:\n /* 5 args: fd, offset (high, low), len, advice */\n- if (regpairs_aligned(cpu_env)) {\n+ if (regpairs_aligned(cpu_env, num)) {\n /* offset is in (3,4), len in 5 and advice in 6 */\n arg2 = arg3;\n arg3 = arg4;\n@@ -11407,7 +11419,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,\n #ifdef TARGET_NR_readahead\n case TARGET_NR_readahead:\n #if TARGET_ABI_BITS == 32\n- if (regpairs_aligned(cpu_env)) {\n+ if (regpairs_aligned(cpu_env, num)) {\n arg2 = arg3;\n arg3 = arg4;\n arg4 = arg5;\n","prefixes":["v2"]}