{"id":814084,"url":"http://patchwork.ozlabs.org/api/patches/814084/?format=json","web_url":"http://patchwork.ozlabs.org/project/netdev/patch/1505457118-3933-1-git-send-email-fahad.kunnathadi@dexceldesigns.com/","project":{"id":7,"url":"http://patchwork.ozlabs.org/api/projects/7/?format=json","name":"Linux network development","link_name":"netdev","list_id":"netdev.vger.kernel.org","list_email":"netdev@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1505457118-3933-1-git-send-email-fahad.kunnathadi@dexceldesigns.com>","list_archive_url":null,"date":"2017-09-15T06:31:58","name":"[net] net: phy: Fix mask value write on gmii2rgmii converter speed register","commit_ref":null,"pull_url":null,"state":"accepted","archived":true,"hash":"e531b20c88b66686b5e5d223ae07aaa878d86afd","submitter":{"id":72361,"url":"http://patchwork.ozlabs.org/api/people/72361/?format=json","name":"Fahad Kunnathadi","email":"fahad.kunnathadi@dexceldesigns.com"},"delegate":{"id":34,"url":"http://patchwork.ozlabs.org/api/users/34/?format=json","username":"davem","first_name":"David","last_name":"Miller","email":"davem@davemloft.net"},"mbox":"http://patchwork.ozlabs.org/project/netdev/patch/1505457118-3933-1-git-send-email-fahad.kunnathadi@dexceldesigns.com/mbox/","series":[{"id":3229,"url":"http://patchwork.ozlabs.org/api/series/3229/?format=json","web_url":"http://patchwork.ozlabs.org/project/netdev/list/?series=3229","date":"2017-09-15T06:31:58","name":"[net] net: phy: Fix mask value write on gmii2rgmii converter speed register","version":1,"mbox":"http://patchwork.ozlabs.org/series/3229/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/814084/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/814084/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"patchwork-incoming@ozlabs.org","Delivered-To":"patchwork-incoming@ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xtlvR4Tbfz9s82\n\tfor ;\n\tFri, 15 Sep 2017 16:32:51 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751330AbdIOGci (ORCPT );\n\tFri, 15 Sep 2017 02:32:38 -0400","from bizsmtp.net4india.com ([118.67.236.10]:43827 \"EHLO\n\tsmtp.bizmail.net4india.com\" rhost-flags-OK-OK-OK-FAIL)\n\tby vger.kernel.org with ESMTP id S1750866AbdIOGch (ORCPT\n\t); Fri, 15 Sep 2017 02:32:37 -0400","from [122.166.48.236] (helo=mailserver.dexceldesigns.com)\n\tby smtp.bizmail.net4india.com with esmtp (Exim 4.72)\n\t(envelope-from )\n\tid 1dskB0-0002Qs-28; Fri, 15 Sep 2017 12:02:34 +0530","from mailserver.dexceldesigns.com (localhost [127.0.0.1])\n\tby mailserver.dexceldesigns.com (Postfix) with ESMTPS id 02C661C01DD3;\n\tFri, 15 Sep 2017 12:00:03 +0530 (IST)","from localhost (localhost [127.0.0.1])\n\tby mailserver.dexceldesigns.com (Postfix) with ESMTP id E4A441CE06E6; \n\tFri, 15 Sep 2017 12:00:02 +0530 (IST)","from mailserver.dexceldesigns.com ([127.0.0.1])\n\tby localhost (mailserver.dexceldesigns.com [127.0.0.1]) (amavisd-new,\n\tport 10026)\n\twith ESMTP id q-ft9xEb1aXc; Fri, 15 Sep 2017 12:00:02 +0530 (IST)","from fahad.domain.dexceldesigns.com (unknown [192.168.0.117])\n\tby mailserver.dexceldesigns.com (Postfix) with ESMTP id C30651C01DD3; \n\tFri, 15 Sep 2017 12:00:02 +0530 (IST)"],"From":"Fahad Kunnathadi ","To":"f.fainelli@gmail.com","Cc":"michal.simek@xilinx.com, davem@davemloft.net, andrew@lunn.ch,\n\tappanad@xilinx.com, soren.brinkmann@xilinx.com,\n\tnetdev@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tFahad Kunnathadi ","Subject":"[PATCH net] net: phy: Fix mask value write on gmii2rgmii converter\n\tspeed register","Date":"Fri, 15 Sep 2017 12:01:58 +0530","Message-Id":"<1505457118-3933-1-git-send-email-fahad.kunnathadi@dexceldesigns.com>","X-Mailer":"git-send-email 1.9.1","Sender":"netdev-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"netdev@vger.kernel.org"},"content":"To clear Speed Selection in MDIO control register(0x10),\nie, clear bits 6 and 13 to zero while keeping other bits same.\nBefore AND operation,The Mask value has to be perform with bitwise NOT\noperation (ie, ~ operator)\n\nThis patch clears current speed selection before writing the\nnew speed settings to gmii2rgmii converter\n\nFixes: f411a6160bd4 (\"net: phy: Add gmiitorgmii converter support\")\n\nSigned-off-by: Fahad Kunnathadi \nReviewed-by: Andrew Lunn \n---\n drivers/net/phy/xilinx_gmii2rgmii.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)","diff":"diff --git a/drivers/net/phy/xilinx_gmii2rgmii.c b/drivers/net/phy/xilinx_gmii2rgmii.c\nindex d15dd39..2e5150b 100644\n--- a/drivers/net/phy/xilinx_gmii2rgmii.c\n+++ b/drivers/net/phy/xilinx_gmii2rgmii.c\n@@ -44,7 +44,7 @@ static int xgmiitorgmii_read_status(struct phy_device *phydev)\n \tpriv->phy_drv->read_status(phydev);\n \n \tval = mdiobus_read(phydev->mdio.bus, priv->addr, XILINX_GMII2RGMII_REG);\n-\tval &= XILINX_GMII2RGMII_SPEED_MASK;\n+\tval &= ~XILINX_GMII2RGMII_SPEED_MASK;\n \n \tif (phydev->speed == SPEED_1000)\n \t\tval |= BMCR_SPEED1000;\n","prefixes":["net"]}