{"id":813343,"url":"http://patchwork.ozlabs.org/api/patches/813343/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1505299969-13329-1-git-send-email-david.wu@rock-chips.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1505299969-13329-1-git-send-email-david.wu@rock-chips.com>","list_archive_url":null,"date":"2017-09-13T10:52:49","name":"[U-Boot,5/8] clk: rockchip: Add rk3328 Saradc clock support","commit_ref":null,"pull_url":null,"state":"superseded","archived":false,"hash":"37842c5657b133ae6918f4d314fd7defb27522f2","submitter":{"id":68083,"url":"http://patchwork.ozlabs.org/api/people/68083/?format=json","name":"David Wu","email":"david.wu@rock-chips.com"},"delegate":{"id":69486,"url":"http://patchwork.ozlabs.org/api/users/69486/?format=json","username":"ptomsich","first_name":"Philipp","last_name":"Tomsich","email":"philipp.tomsich@theobroma-systems.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1505299969-13329-1-git-send-email-david.wu@rock-chips.com/mbox/","series":[{"id":2866,"url":"http://patchwork.ozlabs.org/api/series/2866/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=2866","date":"2017-09-13T10:09:31","name":"Add rockchip Saradc support","version":1,"mbox":"http://patchwork.ozlabs.org/series/2866/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/813343/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/813343/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xsdq00yX0z9sBW\n\tfor ;\n\tWed, 13 Sep 2017 20:55:08 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid D1E92C226EC; Wed, 13 Sep 2017 10:54:19 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id C5C48C225D9;\n\tWed, 13 Sep 2017 10:53:54 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 95BC6C2271F; Wed, 13 Sep 2017 10:53:49 +0000 (UTC)","from lucky1.263xmail.com (lucky1.263xmail.com [211.157.147.133])\n\tby lists.denx.de (Postfix) with ESMTPS id C00ABC22721\n\tfor ; Wed, 13 Sep 2017 10:53:35 +0000 (UTC)","from david.wu?rock-chips.com (unknown [192.168.167.225])\n\tby lucky1.263xmail.com (Postfix) with ESMTP id 3EF528FAE7;\n\tWed, 13 Sep 2017 18:53:31 +0800 (CST)","from localhost.localdomain (localhost [127.0.0.1])\n\tby smtp.263.net (Postfix) with ESMTPA id 28CAB3AE;\n\tWed, 13 Sep 2017 18:53:31 +0800 (CST)","from localhost.localdomain (unknown [58.22.7.114])\n\tby smtp.263.net (Postfix) whith ESMTP id 157450BDBC5;\n\tWed, 13 Sep 2017 18:53:32 +0800 (CST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=0.6 required=5.0 tests=RCVD_IN_MSPIKE_BL,\n\tRCVD_IN_MSPIKE_L4,RCVD_IN_SORBS_WEB autolearn=no autolearn_force=no\n\tversion=3.4.0","X-263anti-spam":"KSV:0;","X-MAIL-GRAY":"1","X-MAIL-DELIVERY":"0","X-KSVirus-check":"0","X-ABS-CHECKED":"4","X-RL-SENDER":"david.wu@rock-chips.com","X-FST-TO":"sjg@chromium.org","X-SENDER-IP":"58.22.7.114","X-LOGIN-NAME":"david.wu@rock-chips.com","X-UNIQUE-TAG":"<88eeaa8984978d9e15fb9984a78e8e38>","X-ATTACHMENT-NUM":"0","X-SENDER":"wdc@rock-chips.com","X-DNS-TYPE":"0","From":"David Wu ","To":"sjg@chromium.org,\n\tphilipp.tomsich@theobroma-systems.com","Date":"Wed, 13 Sep 2017 18:52:49 +0800","Message-Id":"<1505299969-13329-1-git-send-email-david.wu@rock-chips.com>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1505297379-12638-1-git-send-email-david.wu@rock-chips.com>","References":"<1505297379-12638-1-git-send-email-david.wu@rock-chips.com>","Cc":"huangtao@rock-chips.com, u-boot@lists.denx.de, zhangqing@rock-chips.com, \n\tlinux-rockchip@lists.infradead.org, p.marczak@samsung.com,\n\tDavid Wu , andy.yan@rock-chips.com,\n\tchenjh@rock-chips.com","Subject":"[U-Boot] [PATCH 5/8] clk: rockchip: Add rk3328 Saradc clock support","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).\nSaradc integer divider control register is 10-bits width.\n\nSigned-off-by: David Wu \n---\n drivers/clk/rockchip/clk_rk3328.c | 37 +++++++++++++++++++++++++++++++++++++\n 1 file changed, 37 insertions(+)","diff":"diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c\nindex c3a6650..e1ae7b2 100644\n--- a/drivers/clk/rockchip/clk_rk3328.c\n+++ b/drivers/clk/rockchip/clk_rk3328.c\n@@ -115,6 +115,7 @@ enum {\n \t/* CLKSEL_CON23 */\n \tCLK_SARADC_DIV_CON_SHIFT\t= 0,\n \tCLK_SARADC_DIV_CON_MASK\t\t= 0x3ff << CLK_SARADC_DIV_CON_SHIFT,\n+\tCLK_SARADC_DIV_CON_WIDTH\t= 10,\n \n \t/* CLKSEL_CON24 */\n \tCLK_PWM_PLL_SEL_CPLL\t\t= 0,\n@@ -180,6 +181,11 @@ enum {\n #define PLL_DIV_MIN\t16\n #define PLL_DIV_MAX\t3200\n \n+static inline u32 extract_bits(u32 val, unsigned width, unsigned shift)\n+{\n+\treturn (val >> shift) & ((1 << width) - 1);\n+}\n+\n /*\n * How to calculate the PLL(from TRM V0.3 Part 1 Page 63):\n * Formulas also embedded within the Fractional PLL Verilog model:\n@@ -478,6 +484,31 @@ static ulong rk3328_pwm_set_clk(struct rk3328_cru *cru, uint hz)\n \treturn DIV_TO_RATE(GPLL_HZ, div);\n }\n \n+static ulong rk3328_saradc_get_clk(struct rk3328_cru *cru)\n+{\n+\tu32 div, val;\n+\n+\tval = readl(&cru->clksel_con[23]);\n+\tdiv = extract_bits(val, CLK_SARADC_DIV_CON_WIDTH,\n+\t\t\t CLK_SARADC_DIV_CON_SHIFT);\n+\n+\treturn DIV_TO_RATE(OSC_HZ, div);\n+}\n+\n+static ulong rk3328_saradc_set_clk(struct rk3328_cru *cru, uint hz)\n+{\n+\tint src_clk_div;\n+\n+\tsrc_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;\n+\tassert(src_clk_div < 128);\n+\n+\trk_clrsetreg(&cru->clksel_con[23],\n+\t\t CLK_SARADC_DIV_CON_MASK,\n+\t\t src_clk_div << CLK_SARADC_DIV_CON_SHIFT);\n+\n+\treturn rk3328_saradc_get_clk(cru);\n+}\n+\n static ulong rk3328_clk_get_rate(struct clk *clk)\n {\n \tstruct rk3328_clk_priv *priv = dev_get_priv(clk->dev);\n@@ -501,6 +532,9 @@ static ulong rk3328_clk_get_rate(struct clk *clk)\n \tcase SCLK_PWM:\n \t\trate = rk3328_pwm_get_clk(priv->cru);\n \t\tbreak;\n+\tcase SCLK_SARADC:\n+\t\trate = rk3328_saradc_get_clk(priv->cru);\n+\t\tbreak;\n \tdefault:\n \t\treturn -ENOENT;\n \t}\n@@ -531,6 +565,9 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate)\n \tcase SCLK_PWM:\n \t\tret = rk3328_pwm_set_clk(priv->cru, rate);\n \t\tbreak;\n+\tcase SCLK_SARADC:\n+\t\tret = rk3328_saradc_set_clk(priv->cru, rate);\n+\t\tbreak;\n \tdefault:\n \t\treturn -ENOENT;\n \t}\n","prefixes":["U-Boot","5/8"]}