{"id":813308,"url":"http://patchwork.ozlabs.org/api/patches/813308/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1505297379-12638-2-git-send-email-david.wu@rock-chips.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1505297379-12638-2-git-send-email-david.wu@rock-chips.com>","list_archive_url":null,"date":"2017-09-13T10:09:32","name":"[U-Boot,1/8] adc: Add driver for Rockchip Saradc","commit_ref":null,"pull_url":null,"state":"superseded","archived":false,"hash":"0d5a3d6aff5411dbe68743f36902fa62e8f7513a","submitter":{"id":68083,"url":"http://patchwork.ozlabs.org/api/people/68083/?format=json","name":"David Wu","email":"david.wu@rock-chips.com"},"delegate":{"id":69486,"url":"http://patchwork.ozlabs.org/api/users/69486/?format=json","username":"ptomsich","first_name":"Philipp","last_name":"Tomsich","email":"philipp.tomsich@theobroma-systems.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1505297379-12638-2-git-send-email-david.wu@rock-chips.com/mbox/","series":[{"id":2866,"url":"http://patchwork.ozlabs.org/api/series/2866/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=2866","date":"2017-09-13T10:09:31","name":"Add rockchip Saradc support","version":1,"mbox":"http://patchwork.ozlabs.org/series/2866/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/813308/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/813308/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xsctC3n62z9s9Y\n\tfor ;\n\tWed, 13 Sep 2017 20:12:51 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 0351DC2259F; Wed, 13 Sep 2017 10:11:43 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 4ABABC22608;\n\tWed, 13 Sep 2017 10:11:09 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 5B4E6C225E6; Wed, 13 Sep 2017 10:10:55 +0000 (UTC)","from lucky1.263xmail.com (lucky1.263xmail.com [211.157.147.133])\n\tby lists.denx.de (Postfix) with ESMTPS id 93A25C225F9\n\tfor ; Wed, 13 Sep 2017 10:10:54 +0000 (UTC)","from david.wu?rock-chips.com (unknown [192.168.167.229])\n\tby lucky1.263xmail.com (Postfix) with ESMTP id 1E7748F9F9;\n\tWed, 13 Sep 2017 18:10:50 +0800 (CST)","from localhost.localdomain (localhost [127.0.0.1])\n\tby smtp.263.net (Postfix) with ESMTPA id A650D369;\n\tWed, 13 Sep 2017 18:10:49 +0800 (CST)","from unknown (unknown [58.22.7.114])\n\tby smtp.263.net (Postfix) whith SMTP id 15417623RZ0;\n\tWed, 13 Sep 2017 18:10:51 +0800 (CST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=0.6 required=5.0 tests=RCVD_IN_MSPIKE_BL,\n\tRCVD_IN_MSPIKE_L4,RCVD_IN_SORBS_WEB autolearn=no autolearn_force=no\n\tversion=3.4.0","X-263anti-spam":"KSV:0;","X-MAIL-GRAY":"1","X-MAIL-DELIVERY":"0","X-KSVirus-check":"0","X-ABS-CHECKED":"4","X-RL-SENDER":"david.wu@rock-chips.com","X-FST-TO":"sjg@chromium.org","X-SENDER-IP":"58.22.7.114","X-LOGIN-NAME":"david.wu@rock-chips.com","X-UNIQUE-TAG":"<4cffa11d5a86d7df1e0b81015ec63bb1>","X-ATTACHMENT-NUM":"0","X-SENDER":"wdc@rock-chips.com","X-DNS-TYPE":"0","From":"David Wu ","To":"sjg@chromium.org,\n\tphilipp.tomsich@theobroma-systems.com","Date":"Wed, 13 Sep 2017 18:09:32 +0800","Message-Id":"<1505297379-12638-2-git-send-email-david.wu@rock-chips.com>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1505297379-12638-1-git-send-email-david.wu@rock-chips.com>","References":"<1505297379-12638-1-git-send-email-david.wu@rock-chips.com>","Cc":"huangtao@rock-chips.com, u-boot@lists.denx.de, zhangqing@rock-chips.com, \n\tlinux-rockchip@lists.infradead.org, p.marczak@samsung.com,\n\tDavid Wu , andy.yan@rock-chips.com,\n\tchenjh@rock-chips.com","Subject":"[U-Boot] [PATCH 1/8] adc: Add driver for Rockchip Saradc","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"The ADC can support some channels signal-ended some bits Successive Approximation\nRegister (SAR) A/D Converter, like 6-channel and 10-bit. It converts the analog\ninput signal into some bits binary digital codes.\n\nSigned-off-by: David Wu \n---\n drivers/adc/Kconfig | 9 ++\n drivers/adc/Makefile | 1 +\n drivers/adc/rockchip-saradc.c | 188 ++++++++++++++++++++++++++++++++++++++++++\n 3 files changed, 198 insertions(+)\n create mode 100644 drivers/adc/rockchip-saradc.c","diff":"diff --git a/drivers/adc/Kconfig b/drivers/adc/Kconfig\nindex e5335f7..830fe0f 100644\n--- a/drivers/adc/Kconfig\n+++ b/drivers/adc/Kconfig\n@@ -20,6 +20,15 @@ config ADC_EXYNOS\n \t - 12-bit resolution\n \t - 600 KSPS of sample rate\n \n+config SARADC_ROCKCHIP\n+\tbool \"Enable Rockchip SARADC driver\"\n+\thelp\n+\t This enables driver for Rockchip SARADC.\n+\t It provides:\n+\t - 2~6 analog input channels\n+\t - 1O-bit resolution\n+\t - 1MSPS of sample rate\n+\n config ADC_SANDBOX\n \tbool \"Enable Sandbox ADC test driver\"\n \thelp\ndiff --git a/drivers/adc/Makefile b/drivers/adc/Makefile\nindex cebf26d..4b5aa69 100644\n--- a/drivers/adc/Makefile\n+++ b/drivers/adc/Makefile\n@@ -8,3 +8,4 @@\n obj-$(CONFIG_ADC) += adc-uclass.o\n obj-$(CONFIG_ADC_EXYNOS) += exynos-adc.o\n obj-$(CONFIG_ADC_SANDBOX) += sandbox.o\n+obj-$(CONFIG_SARADC_ROCKCHIP) += rockchip-saradc.o\ndiff --git a/drivers/adc/rockchip-saradc.c b/drivers/adc/rockchip-saradc.c\nnew file mode 100644\nindex 0000000..5c7c3d9\n--- /dev/null\n+++ b/drivers/adc/rockchip-saradc.c\n@@ -0,0 +1,188 @@\n+/*\n+ * (C) Copyright 2017, Fuzhou Rockchip Electronics Co., Ltd\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ *\n+ * Rockchip Saradc driver for U-Boot\n+ */\n+\n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+\n+#define SARADC_DATA\t\t\t0x00\n+\n+#define SARADC_STAS\t\t\t0x04\n+#define SARADC_STAS_BUSY\t\tBIT(0)\n+\n+#define SARADC_CTRL\t\t\t0x08\n+#define SARADC_CTRL_POWER_CTRL\t\tBIT(3)\n+#define SARADC_CTRL_CHN_MASK\t\t0x7\n+#define SARADC_CTRL_IRQ_STATUS\t\tBIT(6)\n+#define SARADC_CTRL_IRQ_ENABLE\t\tBIT(5)\n+\n+#define SARADC_DLY_PU_SOC\t\t0x0c\n+\n+#define SARADC_TIMEOUT\t\t\t(100 * 1000)\n+\n+struct rockchip_saradc_data {\n+\tint\t\t\t\tnum_bits;\n+\tint\t\t\t\tnum_channels;\n+\tunsigned long\t\t\tclk_rate;\n+};\n+\n+struct rockchip_saradc_priv {\n+\tfdt_addr_t\t\t\t\tregs;\n+\tint \t\t\t\t\tactive_channel;\n+\tconst struct rockchip_saradc_data\t*data;\n+};\n+\n+int rockchip_saradc_channel_data(struct udevice *dev, int channel,\n+\t\t\t unsigned int *data)\n+{\n+\tstruct rockchip_saradc_priv *priv = dev_get_priv(dev);\n+\n+\tif (channel != priv->active_channel) {\n+\t\terror(\"Requested channel is not active!\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif ((readl(priv->regs + SARADC_CTRL) & SARADC_CTRL_IRQ_STATUS) != SARADC_CTRL_IRQ_STATUS)\n+\t\treturn -EBUSY;\n+\n+\t/* Read value */\n+\t*data = readl(priv->regs + SARADC_DATA);\n+\t*data &= (1 << priv->data->num_bits) - 1;\n+\n+\t/* Power down adc */\n+\twritel(0, priv->regs + SARADC_CTRL);\n+\n+\treturn 0;\n+}\n+\n+int rockchip_saradc_start_channel(struct udevice *dev, int channel)\n+{\n+\tstruct rockchip_saradc_priv *priv = dev_get_priv(dev);\n+\n+\tif (channel < 0 || channel >= priv->data->num_channels) {\n+\t\terror(\"Requested channel is invalid!\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* 8 clock periods as delay between power up and start cmd */\n+\twritel(8, priv->regs + SARADC_DLY_PU_SOC);\n+\n+\t/* Select the channel to be used and trigger conversion */\n+\twritel(SARADC_CTRL_POWER_CTRL\n+\t\t\t| (channel & SARADC_CTRL_CHN_MASK) | SARADC_CTRL_IRQ_ENABLE,\n+\t\t priv->regs + SARADC_CTRL);\n+\n+\tpriv->active_channel = channel;\n+\n+\treturn 0;\n+}\n+\n+int rockchip_saradc_stop(struct udevice *dev)\n+{\n+\tstruct rockchip_saradc_priv *priv = dev_get_priv(dev);\n+\n+\t/* Power down adc */\n+\twritel(0, priv->regs + SARADC_CTRL);\n+\n+\tpriv->active_channel = -1;\n+\n+\treturn 0;\n+}\n+\n+int rockchip_saradc_probe(struct udevice *dev)\n+{\n+\tstruct rockchip_saradc_priv *priv = dev_get_priv(dev);\n+\tstruct clk clk;\n+\tint ret;\n+\n+\tret = clk_get_by_index(dev, 0, &clk);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = clk_set_rate(&clk, priv->data->clk_rate);\n+\tif (IS_ERR_VALUE(ret))\n+\t\treturn ret;\n+\n+\tpriv->active_channel = -1;\n+\n+\treturn 0;\n+}\n+\n+int rockchip_saradc_ofdata_to_platdata(struct udevice *dev)\n+{\n+\tstruct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);\n+\tstruct rockchip_saradc_priv *priv = dev_get_priv(dev);\n+\tstruct rockchip_saradc_data *data =\n+\t\t\t\t\t(struct rockchip_saradc_data *)dev_get_driver_data(dev);\n+\n+\tpriv->regs = devfdt_get_addr(dev);\n+\tif (priv->regs == FDT_ADDR_T_NONE) {\n+\t\terror(\"Dev: %s - can't get address!\", dev->name);\n+\t\treturn -ENODATA;\n+\t}\n+\n+\tpriv->data = data;\n+\tuc_pdata->data_mask = (1 << priv->data->num_bits) - 1;;\n+\tuc_pdata->data_format = ADC_DATA_FORMAT_BIN;\n+\tuc_pdata->data_timeout_us = SARADC_TIMEOUT / 5;\n+\tuc_pdata->channel_mask = (1 << priv->data->num_channels) - 1;\n+\n+\treturn 0;\n+}\n+\n+static const struct adc_ops rockchip_saradc_ops = {\n+\t.start_channel = rockchip_saradc_start_channel,\n+\t.channel_data = rockchip_saradc_channel_data,\n+\t.stop = rockchip_saradc_stop,\n+};\n+\n+static const struct rockchip_saradc_data saradc_data = {\n+\t.num_bits = 10,\n+\t.num_channels = 3,\n+\t.clk_rate = 1000000,\n+};\n+\n+static const struct rockchip_saradc_data rk3066_tsadc_data = {\n+\t.num_bits = 12,\n+\t.num_channels = 2,\n+\t.clk_rate = 50000,\n+};\n+\n+static const struct rockchip_saradc_data rk3399_saradc_data = {\n+\t.num_bits = 10,\n+\t.num_channels = 6,\n+\t.clk_rate = 1000000,\n+};\n+\n+static const struct udevice_id rockchip_saradc_ids[] = {\n+\t{\n+\t\t.compatible = \"rockchip,saradc\",\n+\t\t.data = (ulong)&saradc_data,\n+\t},\n+\t{\n+\t\t.compatible = \"rockchip,rk3066-tsadc\",\n+\t\t.data = (ulong)&rk3066_tsadc_data,\n+\t}, {\n+\t\t.compatible = \"rockchip,rk3399-saradc\",\n+\t\t.data = (ulong)&rk3399_saradc_data,\n+\t},\n+\t{ }\n+};\n+\n+U_BOOT_DRIVER(rockchip_saradc) = {\n+\t.name\t\t= \"rockchip_saradc\",\n+\t.id\t\t= UCLASS_ADC,\n+\t.of_match\t= rockchip_saradc_ids,\n+\t.ops\t\t= &rockchip_saradc_ops,\n+\t.probe\t\t= rockchip_saradc_probe,\n+\t.ofdata_to_platdata = rockchip_saradc_ofdata_to_platdata,\n+\t.priv_auto_alloc_size = sizeof(struct rockchip_saradc_priv),\n+};\n","prefixes":["U-Boot","1/8"]}