{"id":813225,"url":"http://patchwork.ozlabs.org/api/patches/813225/?format=json","web_url":"http://patchwork.ozlabs.org/project/skiboot/patch/20170913085003.9537-1-npiggin@gmail.com/","project":{"id":44,"url":"http://patchwork.ozlabs.org/api/projects/44/?format=json","name":"skiboot firmware development","link_name":"skiboot","list_id":"skiboot.lists.ozlabs.org","list_email":"skiboot@lists.ozlabs.org","web_url":"http://github.com/open-power/skiboot","scm_url":"http://github.com/open-power/skiboot","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170913085003.9537-1-npiggin@gmail.com>","list_archive_url":null,"date":"2017-09-13T08:50:03","name":"core: POWER9 implement OPAL_SIGNAL_SYSTEM_RESET","commit_ref":null,"pull_url":null,"state":"superseded","archived":false,"hash":"a542634c3eaef1f13def379f373b4757e1eca2ab","submitter":{"id":69518,"url":"http://patchwork.ozlabs.org/api/people/69518/?format=json","name":"Nicholas Piggin","email":"npiggin@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/skiboot/patch/20170913085003.9537-1-npiggin@gmail.com/mbox/","series":[{"id":2839,"url":"http://patchwork.ozlabs.org/api/series/2839/?format=json","web_url":"http://patchwork.ozlabs.org/project/skiboot/list/?series=2839","date":"2017-09-13T08:50:03","name":"core: POWER9 implement OPAL_SIGNAL_SYSTEM_RESET","version":1,"mbox":"http://patchwork.ozlabs.org/series/2839/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/813225/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/813225/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","skiboot@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","skiboot@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xsb3K48Kxz9s76\n\tfor ;\n\tWed, 13 Sep 2017 18:50:37 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xsb3K1z4szDq5k\n\tfor ;\n\tWed, 13 Sep 2017 18:50:37 +1000 (AEST)","from mail-pf0-x242.google.com (mail-pf0-x242.google.com\n\t[IPv6:2607:f8b0:400e:c00::242])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xsb2x5jDgzDrJm\n\tfor ; Wed, 13 Sep 2017 18:50:17 +1000 (AEST)","by mail-pf0-x242.google.com with SMTP id q76so7258227pfq.5\n\tfor ; Wed, 13 Sep 2017 01:50:17 -0700 (PDT)","from roar.au.ibm.com (203-219-56-202.tpgi.com.au. [203.219.56.202])\n\tby smtp.gmail.com with ESMTPSA id\n\t20sm24267755pft.109.2017.09.13.01.50.11\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tWed, 13 Sep 2017 01:50:14 -0700 (PDT)"],"Authentication-Results":["ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"pcZNfrOY\"; dkim-atps=neutral","lists.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"pcZNfrOY\"; dkim-atps=neutral","ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gmail.com\n\t(client-ip=2607:f8b0:400e:c00::242; helo=mail-pf0-x242.google.com;\n\tenvelope-from=npiggin@gmail.com; receiver=)","lists.ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"pcZNfrOY\"; dkim-atps=neutral"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=from:to:cc:subject:date:message-id;\n\tbh=v50AqZd2kk5A0Lvzy8/LSLYAUT0R5GNMaRnPVzi4WrQ=;\n\tb=pcZNfrOYQldHFSdDMwDqRA+Q6c33kEwx6yPitmiYYoB6hhkRPwpcInBPtW4WfIWqN/\n\tffFaTrdCcygmrAsYA/a3QYFpIL7Cf0zVfZ+FeJHVnePs4pxM/aiALt4c4emgrTfeJjTN\n\tG084kjkXInD2klxawNpjiWh7uSy4/K+qVMQVKZNXIaBw3/MOwudd3BwnIp/Sqsn4h8oS\n\tP/Q8Rd00dhT19cYB7OXSvJw9Ri7ZuCETRgGFwnvWByJqrgGSIX/j6EjBGIqlZynvWbUq\n\tmSK363HW/KWVXYNMvIbAC8yyeSpV+TVVHzF1MnuCvA6sldx5ItCC6RwxvenYsJFHdEpH\n\tRtoQ==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id;\n\tbh=v50AqZd2kk5A0Lvzy8/LSLYAUT0R5GNMaRnPVzi4WrQ=;\n\tb=GJvqRPylr4w1GYTF5r6WTsKZMzOJLOjyOwDGlkrthbiT4qedFgRtNv/HEsFZQBdhjQ\n\tg+hn098vCEm/CiR8uOyVuzca4ikMoCLV1Dj9i3iADzinQ0XQD/Zbles6R10fd2/7tkLV\n\t/l41tl6Wjs/c0psvDcctNPjsukC4omZMxCSByQ2sZHL9Hz50j3G98osuUt5VxBqvbu9d\n\t6I1WjvZ+zgfZUDUUobfx5Yt2A2XWcJTWN0+SjnEgKEPeXigDGY0Xr/8JAk7OyyD+DMWV\n\t7KamnKxhYGaFgAC6W9xNZ65ePoBnJeYx/XWq6WyglmgZAp3d3LAnJOsMkbfnFtj+twkb\n\tXuMg==","X-Gm-Message-State":"AHPjjUjfTwK9HhXPZ4ijoW5Bz/W8B0W0AVJx1I5Roa4ahpjYsRu9z5UH\n\t+Lr9XuNyem9Osd3X","X-Google-Smtp-Source":"ADKCNb7jgzEVzAxyd58jfPaHQX9cX3eNSyBUqT65A/NA3/geg2UlHaHUc5uAwlHQvp4oq4wKvZDmbQ==","X-Received":"by 10.98.15.208 with SMTP id 77mr17486184pfp.318.1505292615153; \n\tWed, 13 Sep 2017 01:50:15 -0700 (PDT)","From":"Nicholas Piggin ","To":"skiboot@lists.ozlabs.org","Date":"Wed, 13 Sep 2017 18:50:03 +1000","Message-Id":"<20170913085003.9537-1-npiggin@gmail.com>","X-Mailer":"git-send-email 2.13.3","Subject":"[Skiboot] [PATCH] core: POWER9 implement OPAL_SIGNAL_SYSTEM_RESET","X-BeenThere":"skiboot@lists.ozlabs.org","X-Mailman-Version":"2.1.24","Precedence":"list","List-Id":"Mailing list for skiboot development ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Alistair Popple ","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org","Sender":"\"Skiboot\"\n\t"},"content":"This implements OPAL_SIGNAL_SYSTEM_RESET, using scom registers to\nquiesce the target thread and raise a system reset exception on it.\n\nThis has been tested on DD1 and DD2 including ESL=1 power saving modes.\nIt has not yet been tested with deep idle states, because those have\nnot yet been enabled. If those cannot be supported, it should be\npossible to query PSSCR[PLS] from scoms and fail in that case (Linux\ncould fall back to a doorbell).\n\nSigned-off-by: Nicholas Piggin \n---\nThis is now tested and seems to be working fine on a DD2. Only\nchanges since last post are to add documentation and tidy up the\nconstants and things a bit.\n\nWith this patch and some enablement, Linux is able to detect hard\nlocked (MSR[EE]=0) threads and get stack traces from them, bring\nthem into xmon or panic and restart the box, etc. Here is a test case\nwhere CPU60 disables interrupts then spins, with hardlockup_panic=1:\n\nWatchdog CPU:64 detected Hard LOCKUP other CPUS:60\nWatchdog CPU:60 Hard LOCKUP\nModules linked in: iptable_mangle ipt_MASQUERADE nf_nat_masquerade_ipv4 iptable_nat nf_nat_ipv4 nf_nat nf_conntrack_ipv4 nf_defrag_ipv4 xt_conntrack nf_conntrack ipt_REJECT nf_reject_ipv4 xt_tcpudp tun bridge stp llc kvm_hv kvm iptable_filter ib_ipoib ib_cm ib_core vmx_crypto binfmt_misc dm_multipath scsi_dh_rdac scsi_dh_alua ip_tables x_tables autofs4 crc32c_vpmsum\nCPU: 60 PID: 4918 Comm: bash Not tainted 4.13.0-11559-g6d8ef53e8b2f-dirty #10\ntask: c000000f15a61600 task.stack: c000000f144fc000\nNIP: c0000000000aa81c LR: c0000000000accc8 CTR: c0000000000aa800\nREGS: c00000003fd2bd80 TRAP: 0100 Not tainted (4.13.0-11559-g6d8ef53e8b2f-dirty)\nMSR: 9000000000081033 CR: 28422228 XER: 20040000\nCFAR: c0000000000aa81c SOFTE: 0 \nGPR00: c000000000638bf8 c000000f144ffba0 c00000000106c000 0000000000000000 \nGPR04: c00000000109bac8 c0000000000b1710 c00000000109bae0 c0000000000b1690 \nGPR08: 0000000000000000 c000000000f0fcf0 0000000000000001 c00000000109bad0 \nGPR12: c0000000000aa800 c00000000fd54a00 0000000010180df8 0000000010189e60 \nGPR16: 0000000010189ed8 0000000010151270 000000001018bd88 000000001018de78 \nGPR20: 0000000038147048 0000000000000001 00000000101645e0 0000000010163c10 \nGPR24: 00007ffff6f9efb4 00007ffff6f9efb0 c000000000fab868 0000000000000004 \nGPR28: c000000000f254b8 0000000000000078 c000000000f30dbc c00000000109bac0 \nNIP [c0000000000aa81c] xmon+0x1c/0x20\nLR [c0000000000accc8] sysrq_handle_xmon+0xc8/0xd0\nCall Trace:\n[c000000f144ffba0] [c00000000014c584] printk+0x48/0x5c (unreliable)\n[c000000f144ffbd0] [c000000000638bf8] __handle_sysrq+0xe8/0x280\n[c000000f144ffc70] [c0000000006393a8] write_sysrq_trigger+0x78/0xa0\n[c000000f144ffca0] [c0000000003c93d0] proc_reg_write+0xb0/0x110\n[c000000f144ffcf0] [c00000000033555c] __vfs_write+0x6c/0x1d0\n[c000000f144ffd90] [c000000000337434] vfs_write+0xd4/0x240\n[c000000f144ffde0] [c00000000033932c] SyS_write+0x6c/0x110\n[c000000f144ffe30] [c00000000000b220] system_call+0x58/0x6c\nInstruction dump:\n4e800020 00000000 00000000 00000000 00000000 e94d0020 7d410164 894d027b \n39000000 990d027a 614a0001 994d027b <48000000> 3c4c00fc 384217e0 2ba30980 \nKernel panic - not syncing: Hard LOCKUP\nCPU: 64 PID: 0 Comm: swapper/64 Not tainted 4.13.0-11559-g6d8ef53e8b2f-dirty #10\nCall Trace:\n[c000000f229ab560] [c000000000ae31d0] dump_stack+0xb0/0xf0 (unreliable)\n[c000000f229ab5a0] [c0000000000d3d3c] panic+0x164/0x408\n[c000000f229ab640] [c0000000000d3764] nmi_panic+0xa4/0xb0\n[c000000f229ab6b0] [c00000000002f700] watchdog_timer_interrupt+0x380/0x390\n[c000000f229ab760] [c00000000002f7e0] wd_timer_fn+0x40/0x60\n[c000000f229ab790] [c000000000172574] call_timer_fn+0x64/0x1d0\n[c000000f229ab820] [c000000000172860] expire_timers+0x140/0x1e0\n[c000000f229ab890] [c0000000001729d8] run_timer_softirq+0xd8/0x240\n[c000000f229ab920] [c000000000b04410] __do_softirq+0x180/0x3f8\n[c000000f229aba20] [c0000000000dbec8] irq_exit+0xf8/0x130\n[c000000f229aba40] [c0000000000250c4] timer_interrupt+0xa4/0x110\n[c000000f229aba80] [c000000000009018] decrementer_common+0x128/0x130\n--- interrupt: 901 at snooze_loop+0xac/0x190\n LR = snooze_loop+0x170/0x190\n[c000000f229abd70] [c000000f229abdb0] 0xc000000f229abdb0 (unreliable)\n[c000000f229abdb0] [c00000000094270c] cpuidle_enter_state+0x16c/0x450\n[c000000f229abe10] [c000000000135b40] call_cpuidle+0x70/0xd0\n[c000000f229abe50] [c000000000135f88] do_idle+0x1f8/0x2c0\n[c000000f229abec0] [c000000000136278] cpu_startup_entry+0x38/0x40\n[c000000f229abef0] [c000000000040a10] start_secondary+0x4c0/0x4f0\n[c000000f229abf90] [c00000000000ab6c] start_secondary_prolog+0x10/0x14\nRebooting in 10 seconds..\n\n*** snip pages of \"Trying to free IRQ blah from IRQ context!\" ***\n\n--== Welcome to Hostboot hostboot-c68be97/hbicore.bin ==--\n...\n\n\n core/Makefile.inc | 1 +\n core/sreset.c | 261 ++++++++++++++++++++++++++\n doc/opal-api/opal-signal-system-reset-145.rst | 23 ++-\n hw/xscom.c | 4 +\n include/skiboot.h | 3 +\n 5 files changed, 282 insertions(+), 10 deletions(-)\n create mode 100644 core/sreset.c","diff":"diff --git a/core/Makefile.inc b/core/Makefile.inc\nindex f2de2f64..16204978 100644\n--- a/core/Makefile.inc\n+++ b/core/Makefile.inc\n@@ -9,6 +9,7 @@ CORE_OBJS += vpd.o hostservices.o platform.o nvram.o nvram-format.o hmi.o\n CORE_OBJS += console-log.o ipmi.o time-utils.o pel.o pool.o errorlog.o\n CORE_OBJS += timer.o i2c.o rtc.o flash.o sensor.o ipmi-opal.o\n CORE_OBJS += flash-subpartition.o bitmap.o buddy.o pci-quirk.o powercap.o psr.o\n+CORE_OBJS += sreset.o\n \n ifeq ($(SKIBOOT_GCOV),1)\n CORE_OBJS += gcov-profiling.o\ndiff --git a/core/sreset.c b/core/sreset.c\nnew file mode 100644\nindex 00000000..5081e1c2\n--- /dev/null\n+++ b/core/sreset.c\n@@ -0,0 +1,261 @@\n+/* Copyright 2017 IBM Corp.\n+ *\n+ * Licensed under the Apache License, Version 2.0 (the \"License\");\n+ * you may not use this file except in compliance with the License.\n+ * You may obtain a copy of the License at\n+ *\n+ * \thttp://www.apache.org/licenses/LICENSE-2.0\n+ *\n+ * Unless required by applicable law or agreed to in writing, software\n+ * distributed under the License is distributed on an \"AS IS\" BASIS,\n+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or\n+ * implied.\n+ * See the License for the specific language governing permissions and\n+ * limitations under the License.\n+ */\n+\n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+\n+#define P9_RAS_STATUS\t\t\t0x10a02\n+#define P9_RSTAT_QUIESCED(t)\t\tPPC_BITMASK(0 + 8*(t), 3 + 8*(t))\n+#define P9_RSTAT_RETRIES\t\t100\n+\n+#define P9_RAS_MODEREG\t\t\t0x10a9d\n+#define P9_DIRECT_CONTROLS\t\t0x10a9c\n+#define P9_DCTL_STOP(t)\t\t\tPPC_BIT(7 + 8*(t))\n+#define P9_DCTL_CONT(t)\t\t\tPPC_BIT(6 + 8*(t))\n+#define P9_DCTL_SRESET(t)\t\tPPC_BIT(4 + 8*(t))\n+#define P9_DCTL_PWR(t)\t\t\tPPC_BIT(32 + 8*(t))\n+\n+#define P9_CORE_THREAD_STATE\t\t0x10ab3\n+#define P9_CTS_STOP(t)\t\t\tPPC_BIT(56 + (t))\n+\n+#define P9_PPM_GPMMR\t\t\t0xf0100\n+#define P9_GPMMR_SPWKUP_DONE\t\tPPC_BIT(1)\n+#define P9_GPMMR_SPWKUP_TIMEOUT\t\t10\n+\n+#define P9_PPM_SPWKUP_OTR\t\t0xf010a\n+#define P9_SPWKUP_SET\t\t\tPPC_BIT(0)\n+\n+\n+static int core_set_special_wakeup(struct cpu_thread *cpu)\n+{\n+\tuint32_t chip_id = pir_to_chip_id(cpu->pir);\n+\tuint32_t core_id = pir_to_core_id(cpu->pir);\n+\tuint32_t swake_addr;\n+\tuint32_t gpmmr_addr;\n+\tuint64_t val;\n+\tint i;\n+\n+\tswake_addr = XSCOM_ADDR_P9_EC(core_id, P9_PPM_SPWKUP_OTR);\n+\tgpmmr_addr = XSCOM_ADDR_P9_EC(core_id, P9_PPM_GPMMR);\n+\n+\t/*\n+\t * The read-write-read pattern with read errors ignored comes from\n+\t * P8 code. This should be revisited, but it does not appear to have\n+\t * any ill effects.\n+\t */\n+\txscom_read(chip_id, swake_addr, &val);\n+\tif (xscom_write(chip_id, swake_addr, P9_SPWKUP_SET)) {\n+\t\tprlog(PR_WARNING, \"SRESET: Unable to write SPWKUP_OTR register\\n\");\n+\t\treturn OPAL_HARDWARE;\n+\t}\n+\txscom_read(chip_id, swake_addr, &val);\n+\n+\tfor (i = 0; i < P9_GPMMR_SPWKUP_TIMEOUT; i++) {\n+\t\tif (xscom_read(chip_id, gpmmr_addr, &val)) {\n+\t\t\tprlog(PR_WARNING, \"SRESET: Unable to read GPMMR register\\n\");\n+\t\t\treturn OPAL_HARDWARE;\n+\t\t}\n+\t\tif (val & P9_GPMMR_SPWKUP_DONE)\n+\t\t\treturn 0;\n+\n+\t\ttime_wait_us(1);\n+\t}\n+\n+\t/* De-assert special wakeup bit */\n+\txscom_read(chip_id, swake_addr, &val);\n+\txscom_write(chip_id, swake_addr, 0);\n+\txscom_read(chip_id, swake_addr, &val);\n+\n+\tprlog(PR_WARNING, \"SRESET: Special wakeup mode could not be set.\\n\");\n+\treturn OPAL_HARDWARE;\n+}\n+\n+static void core_clear_special_wakeup(struct cpu_thread *cpu)\n+{\n+\tuint32_t chip_id = pir_to_chip_id(cpu->pir);\n+\tuint32_t core_id = pir_to_core_id(cpu->pir);\n+\tuint32_t swake_addr;\n+\tuint64_t val;\n+\n+\tswake_addr = XSCOM_ADDR_P9_EC(core_id, P9_PPM_SPWKUP_OTR);\n+\n+\t/* De-assert special wakeup bit */\n+\txscom_read(chip_id, swake_addr, &val);\n+\txscom_write(chip_id, swake_addr, 0);\n+\txscom_read(chip_id, swake_addr, &val);\n+}\n+\n+static int thread_quiesced(struct cpu_thread *cpu)\n+{\n+\tuint32_t chip_id = pir_to_chip_id(cpu->pir);\n+\tuint32_t core_id = pir_to_core_id(cpu->pir);\n+\tuint32_t thread_id = pir_to_thread_id(cpu->pir);\n+\tuint32_t ras_addr;\n+\tuint64_t ras_status;\n+\n+\tras_addr = XSCOM_ADDR_P9_EC(core_id, P9_RAS_STATUS);\n+\tif (xscom_read(chip_id, ras_addr, &ras_status)) {\n+\t\tprlog(PR_WARNING, \"SRESET: Unable to read status register\\n\");\n+\t\treturn OPAL_HARDWARE;\n+\t}\n+\n+\tif ((ras_status & P9_RSTAT_QUIESCED(thread_id))\n+\t\t\t== P9_RSTAT_QUIESCED(thread_id))\n+\t\treturn 1;\n+\n+\treturn 0;\n+}\n+\n+static int stop_thread(struct cpu_thread *cpu)\n+{\n+\tuint32_t chip_id = pir_to_chip_id(cpu->pir);\n+\tuint32_t core_id = pir_to_core_id(cpu->pir);\n+\tuint32_t thread_id = pir_to_thread_id(cpu->pir);\n+\tuint32_t dctl_addr;\n+\tint i;\n+\n+\tdctl_addr = XSCOM_ADDR_P9_EC(core_id, P9_DIRECT_CONTROLS);\n+\n+\txscom_write(chip_id, dctl_addr, P9_DCTL_STOP(thread_id));\n+\n+\tfor (i = 0; i < P9_RSTAT_RETRIES; i++) {\n+\t\tint rc = thread_quiesced(cpu);\n+\t\tif (rc < 0)\n+\t\t\tbreak;\n+\t\tif (rc)\n+\t\t\treturn 0;\n+\t}\n+\n+\txscom_write(chip_id, dctl_addr, P9_DCTL_CONT(thread_id));\n+\tprlog(PR_WARNING, \"SRESET: Could not quiesce thread\\n\");\n+\treturn OPAL_HARDWARE;\n+}\n+\n+static int sreset_thread(struct cpu_thread *cpu)\n+{\n+\tuint32_t chip_id = pir_to_chip_id(cpu->pir);\n+\tuint32_t core_id = pir_to_core_id(cpu->pir);\n+\tuint32_t thread_id = pir_to_thread_id(cpu->pir);\n+\tuint32_t dctl_addr;\n+\tuint32_t cts_addr;\n+\tuint64_t cts_val;\n+\n+\tdctl_addr = XSCOM_ADDR_P9_EC(core_id, P9_DIRECT_CONTROLS);\n+\tcts_addr = XSCOM_ADDR_P9_EC(core_id, P9_CORE_THREAD_STATE);\n+\n+\tif (xscom_read(chip_id, cts_addr, &cts_val)) {\n+\t\tprlog(PR_WARNING, \"SRESET: Unable to read CORE_THREAD_STATE register\\n\");\n+\t\treturn OPAL_HARDWARE;\n+\t}\n+\tif (!(cts_val & P9_CTS_STOP(thread_id))) {\n+\t\t/*\n+\t\t * Quiescing a thread causes SRR1[46:47] to be set by the\n+\t\t * system reset interrupt as though it was in a power saving\n+\t\t * mode even if it was not.\n+\t\t *\n+\t\t * Setting the DCTL_PWR bit causes SRR1[46:47] to be clear,\n+\t\t * so poke that if thread state says we were in stop.\n+\t\t */\n+\t\tif (xscom_write(chip_id, dctl_addr, P9_DCTL_PWR(thread_id))) {\n+\t\t\tprlog(PR_WARNING, \"SRESET: Unable to set power saving mode\\n\");\n+\t\t\treturn OPAL_HARDWARE;\n+\t\t}\n+\t}\n+\n+\tif (xscom_write(chip_id, dctl_addr, P9_DCTL_SRESET(thread_id))) {\n+\t\tprlog(PR_WARNING, \"SRESET: Unable to write DIRECT_CONTROLS register\\n\");\n+\t\treturn OPAL_HARDWARE;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int64_t sreset_cpu(struct cpu_thread *cpu)\n+{\n+\tint rc;\n+\n+\tif (this_cpu() == cpu) {\n+\t\tprlog(PR_WARNING, \"SRESET: Unable to reset self\\n\");\n+\t\treturn OPAL_UNSUPPORTED;\n+\t}\n+\tif (this_cpu()->primary == cpu->primary) {\n+\t\tprlog(PR_WARNING, \"SRESET: Unable to reset threads on same core\\n\");\n+\t\treturn OPAL_PARTIAL;\n+\t}\n+\n+\trc = thread_quiesced(cpu);\n+\tif (rc < 0)\n+\t\treturn rc;\n+\tif (rc) {\n+\t\tprlog(PR_WARNING, \"SRESET: Thread is quiesced already\\n\");\n+\t\treturn OPAL_WRONG_STATE;\n+\t}\n+\n+\trc = core_set_special_wakeup(cpu);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\trc = stop_thread(cpu);\n+\tif (rc) {\n+\t\tcore_clear_special_wakeup(cpu);\n+\t\treturn rc;\n+\t}\n+\n+\trc = sreset_thread(cpu);\n+\n+\tcore_clear_special_wakeup(cpu);\n+\n+\treturn 0;\n+}\n+\n+static struct lock sreset_lock = LOCK_UNLOCKED;\n+\n+int64_t signal_system_reset(int cpu_nr)\n+{\n+\tstruct cpu_thread *cpu;\n+\tint64_t ret;\n+\n+\tif (proc_gen != proc_gen_p9)\n+\t\treturn OPAL_UNSUPPORTED;\n+\n+\t/* Broadcasts unsupported because we can't signal siblings */\n+\tif (cpu_nr < 0)\n+\t\treturn OPAL_PARTIAL;\n+\n+\t/* Reset a single CPU */\n+\tcpu = find_cpu_by_server(cpu_nr);\n+\tif (!cpu) {\n+\t\tprlog(PR_WARNING, \"SRESET: could not find cpu by server %d\\n\", cpu_nr);\n+\t\treturn OPAL_PARAMETER;\n+\t}\n+\n+\tlock(&sreset_lock);\n+\tret = sreset_cpu(cpu);\n+\tunlock(&sreset_lock);\n+\n+\treturn ret;\n+}\ndiff --git a/doc/opal-api/opal-signal-system-reset-145.rst b/doc/opal-api/opal-signal-system-reset-145.rst\nindex 3ddb6845..6fc7a20b 100644\n--- a/doc/opal-api/opal-signal-system-reset-145.rst\n+++ b/doc/opal-api/opal-signal-system-reset-145.rst\n@@ -9,12 +9,13 @@ OPAL_SIGNAL_SYSTEM_RESET\n This OPAL call causes the specified cpu(s) to be reset to the system\n reset exception handler (0x100).\n \n-The exact contents of system registers (e.g., SRR1 wakeup causes) may\n-vary depending on implementation and should not be relied upon.\n+The SRR1 register will indicate a power-saving wakeup when appropriate,\n+and the wake reason will be System Reset (see Power ISA).\n \n-Resetting active threads on the same core as this call is run may\n-not be supported by some platforms. In that case, OPAL_PARTIAL will be\n-returned and NONE of the interrupts will be delivered.\n+This interrupt may not be recoverable in some cases (e.g., if it is\n+raised when the target has MSR[RI]=0), so it should not be used in\n+normal operation, but only for crashing, debugging, and similar\n+exceptional cases.\n \n Arguments\n ---------\n@@ -28,18 +29,20 @@ Arguments\n Returns\n -------\n OPAL_SUCCESS\n- The power down was updated successful.\n+ The system reset requests to target CPU(s) was successful. This returns\n+ asynchronously without acknowledgement that system reset interrupt\n+ processing has completed or even started.\n \n OPAL_PARAMETER\n A parameter was incorrect.\n \n OPAL_HARDWARE\n- Hardware indicated failure during reset.\n+ Hardware indicated failure during reset, some or all of the target CPUs\n+ may have the system reset delivered.\n \n OPAL_PARTIAL\n- Platform can not reset all requested CPUs at this time. This requires\n- platform-specific code to work around, otherwise to be treated as\n- failure. No CPUs are reset.\n+ Platform can not reset sibling threads on the same core as requested.\n+ None of the specified CPUs are reset in this case.\n \n OPAL_UNSUPPORTED\n This processor/platform is not supported.\ndiff --git a/hw/xscom.c b/hw/xscom.c\nindex 7bd78bf9..4a6d91f4 100644\n--- a/hw/xscom.c\n+++ b/hw/xscom.c\n@@ -705,6 +705,10 @@ static void xscom_init_chip_info(struct proc_chip *chip)\n \t\tprintf(\"P9 DD%i.%i%d detected\\n\", 0xf & (chip->ec_level >> 4),\n \t\t chip->ec_level & 0xf, rev);\n \t\tchip->ec_rev = rev;\n+\n+\t\tif (!chip_quirk(QUIRK_MAMBO_CALLOUTS))\n+\t\t\topal_register(OPAL_SIGNAL_SYSTEM_RESET,\n+\t\t\t\t\tsignal_system_reset, 1);\n \t}\n }\n \ndiff --git a/include/skiboot.h b/include/skiboot.h\nindex 0ab9f388..55aa9b8e 100644\n--- a/include/skiboot.h\n+++ b/include/skiboot.h\n@@ -198,6 +198,9 @@ extern char __sym_map_end[];\n extern unsigned long get_symbol(unsigned long addr,\n \t\t\t\tchar **sym, char **sym_end);\n \n+/* System reset */\n+extern int64_t signal_system_reset(int cpu_nr);\n+\n /* Fast reboot support */\n extern void disable_fast_reboot(const char *reason);\n extern void fast_reboot(void);\n","prefixes":[]}