{"id":813004,"url":"http://patchwork.ozlabs.org/api/patches/813004/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-14-git-send-email-peter.maydell@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1505240046-11454-14-git-send-email-peter.maydell@linaro.org>","list_archive_url":null,"date":"2017-09-12T18:14:00","name":"[13/19] nvic: Implement v8M changes to fixed priority exceptions","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"4dcdec254f51e36fe393a04d3357ee3d2274e550","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-14-git-send-email-peter.maydell@linaro.org/mbox/","series":[{"id":2751,"url":"http://patchwork.ozlabs.org/api/series/2751/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2751","date":"2017-09-12T18:13:53","name":"ARMv8M: support security extn in the NVIC","version":1,"mbox":"http://patchwork.ozlabs.org/series/2751/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/813004/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/813004/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xsCxF2wnkz9s8J\n\tfor ;\n\tWed, 13 Sep 2017 04:29:04 +1000 (AEST)","from localhost ([::1]:38023 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1drpvf-00017h-LT\n\tfor incoming@patchwork.ozlabs.org; Tue, 12 Sep 2017 14:28:59 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:43576)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1drph6-0003X3-5f\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 14:13:57 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1drph4-0006UU-JY\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 14:13:56 -0400","from orth.archaic.org.uk ([2001:8b0:1d0::2]:37316)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1drph1-0006QF-4q; Tue, 12 Sep 2017 14:13:51 -0400","from pm215 by orth.archaic.org.uk with local (Exim 4.89)\n\t(envelope-from )\n\tid 1drpgy-00018i-Ao; Tue, 12 Sep 2017 19:13:48 +0100"],"From":"Peter Maydell ","To":"qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org","Date":"Tue, 12 Sep 2017 19:14:00 +0100","Message-Id":"<1505240046-11454-14-git-send-email-peter.maydell@linaro.org>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1505240046-11454-1-git-send-email-peter.maydell@linaro.org>","References":"<1505240046-11454-1-git-send-email-peter.maydell@linaro.org>","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2001:8b0:1d0::2","Subject":"[Qemu-devel] [PATCH 13/19] nvic: Implement v8M changes to fixed\n\tpriority exceptions","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"patches@linaro.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"In v7M, the fixed-priority exceptions are:\n Reset: -3\n NMI: -2\n HardFault: -1\n\nIn v8M, this changes because Secure HardFault may need\nto be prioritised above NMI:\n Reset: -4\n Secure HardFault if AIRCR.BFHFNMINS == 1: -3\n NMI: -2\n Secure HardFault if AIRCR.BFHFNMINS == 0: -1\n NonSecure HardFault: -1\n\nMake these changes, including support for changing the\npriority of Secure HardFault as AIRCR.BFHFNMINS changes.\n\nSigned-off-by: Peter Maydell \n---\n hw/intc/armv7m_nvic.c | 22 +++++++++++++++++++---\n 1 file changed, 19 insertions(+), 3 deletions(-)","diff":"diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c\nindex c4670f7..db2f170 100644\n--- a/hw/intc/armv7m_nvic.c\n+++ b/hw/intc/armv7m_nvic.c\n@@ -937,6 +937,12 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,\n (R_V7M_AIRCR_SYSRESETREQS_MASK |\n R_V7M_AIRCR_BFHFNMINS_MASK |\n R_V7M_AIRCR_PRIS_MASK);\n+ /* BFHFNMINS changes the priority of Secure HardFault */\n+ if (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) {\n+ s->sec_vectors[ARMV7M_EXCP_HARD].prio = -3;\n+ } else {\n+ s->sec_vectors[ARMV7M_EXCP_HARD].prio = -1;\n+ }\n }\n nvic_irq_update(s);\n }\n@@ -1452,9 +1458,12 @@ static int nvic_post_load(void *opaque, int version_id)\n {\n NVICState *s = opaque;\n unsigned i;\n+ int resetprio;\n \n /* Check for out of range priority settings */\n- if (s->vectors[ARMV7M_EXCP_RESET].prio != -3 ||\n+ resetprio = arm_feature(&s->cpu->env, ARM_FEATURE_V8) ? -4 : -3;\n+\n+ if (s->vectors[ARMV7M_EXCP_RESET].prio != resetprio ||\n s->vectors[ARMV7M_EXCP_NMI].prio != -2 ||\n s->vectors[ARMV7M_EXCP_HARD].prio != -1) {\n return 1;\n@@ -1497,7 +1506,12 @@ static int nvic_security_post_load(void *opaque, int version_id)\n int i;\n \n /* Check for out of range priority settings */\n- if (s->sec_vectors[ARMV7M_EXCP_HARD].prio != -1) {\n+ if (s->sec_vectors[ARMV7M_EXCP_HARD].prio != -1\n+ && s->sec_vectors[ARMV7M_EXCP_HARD].prio != -3) {\n+ /* We can't cross-check against AIRCR.BFHFNMINS as we don't know\n+ * if the CPU state has been migrated yet; a mismatch won't\n+ * cause the emulation to blow up, though.\n+ */\n return 1;\n }\n for (i = ARMV7M_EXCP_MEM; i < ARRAY_SIZE(s->sec_vectors); i++) {\n@@ -1544,6 +1558,7 @@ static Property props_nvic[] = {\n \n static void armv7m_nvic_reset(DeviceState *dev)\n {\n+ int resetprio;\n NVICState *s = NVIC(dev);\n \n s->vectors[ARMV7M_EXCP_NMI].enabled = 1;\n@@ -1556,7 +1571,8 @@ static void armv7m_nvic_reset(DeviceState *dev)\n s->vectors[ARMV7M_EXCP_PENDSV].enabled = 1;\n s->vectors[ARMV7M_EXCP_SYSTICK].enabled = 1;\n \n- s->vectors[ARMV7M_EXCP_RESET].prio = -3;\n+ resetprio = arm_feature(&s->cpu->env, ARM_FEATURE_V8) ? -4 : -3;\n+ s->vectors[ARMV7M_EXCP_RESET].prio = resetprio;\n s->vectors[ARMV7M_EXCP_NMI].prio = -2;\n s->vectors[ARMV7M_EXCP_HARD].prio = -1;\n \n","prefixes":["13/19"]}