{"id":813003,"url":"http://patchwork.ozlabs.org/api/patches/813003/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-11-git-send-email-peter.maydell@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1505240046-11454-11-git-send-email-peter.maydell@linaro.org>","list_archive_url":null,"date":"2017-09-12T18:13:57","name":"[10/19] nvic: Make SHPR registers banked","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"5ed1a934f89925e20e0e99c45243bc69c199f4d6","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-11-git-send-email-peter.maydell@linaro.org/mbox/","series":[{"id":2751,"url":"http://patchwork.ozlabs.org/api/series/2751/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2751","date":"2017-09-12T18:13:53","name":"ARMv8M: support security extn in the NVIC","version":1,"mbox":"http://patchwork.ozlabs.org/series/2751/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/813003/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/813003/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xsCtM1Tldz9s8J\n\tfor ;\n\tWed, 13 Sep 2017 04:26:35 +1000 (AEST)","from localhost ([::1]:38013 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1drptJ-00077E-59\n\tfor incoming@patchwork.ozlabs.org; Tue, 12 Sep 2017 14:26:33 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:43515)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1drph4-0003V1-VD\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 14:13:56 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1drph2-0006SZ-Lx\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 14:13:54 -0400","from orth.archaic.org.uk ([2001:8b0:1d0::2]:37306)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1drpgx-0006O6-EL; Tue, 12 Sep 2017 14:13:47 -0400","from pm215 by orth.archaic.org.uk with local (Exim 4.89)\n\t(envelope-from )\n\tid 1drpgw-000170-Bd; Tue, 12 Sep 2017 19:13:46 +0100"],"From":"Peter Maydell ","To":"qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org","Date":"Tue, 12 Sep 2017 19:13:57 +0100","Message-Id":"<1505240046-11454-11-git-send-email-peter.maydell@linaro.org>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1505240046-11454-1-git-send-email-peter.maydell@linaro.org>","References":"<1505240046-11454-1-git-send-email-peter.maydell@linaro.org>","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2001:8b0:1d0::2","Subject":"[Qemu-devel] [PATCH 10/19] nvic: Make SHPR registers banked","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"patches@linaro.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"Make the set_prio() function take a bool indicating\nwhether to pend the secure or non-secure version of a banked\ninterrupt, and use this to implement the correct banking\nsemantics for the SHPR registers.\n\nSigned-off-by: Peter Maydell \n---\n hw/intc/armv7m_nvic.c | 96 ++++++++++++++++++++++++++++++++++++++++++++++-----\n hw/intc/trace-events | 2 +-\n 2 files changed, 88 insertions(+), 10 deletions(-)","diff":"diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c\nindex 852db11..00c03b4 100644\n--- a/hw/intc/armv7m_nvic.c\n+++ b/hw/intc/armv7m_nvic.c\n@@ -349,15 +349,40 @@ int armv7m_nvic_raw_execution_priority(void *opaque)\n return s->exception_prio;\n }\n \n-/* caller must call nvic_irq_update() after this */\n-static void set_prio(NVICState *s, unsigned irq, uint8_t prio)\n+/* caller must call nvic_irq_update() after this.\n+ * secure indicates the bank to use for banked exceptions (we assert if\n+ * we are passed secure=true for a non-banked exception).\n+ */\n+static void set_prio(NVICState *s, unsigned irq, bool secure, uint8_t prio)\n {\n assert(irq > ARMV7M_EXCP_NMI); /* only use for configurable prios */\n assert(irq < s->num_irq);\n \n- s->vectors[irq].prio = prio;\n+ if (secure) {\n+ assert(exc_is_banked(irq));\n+ s->sec_vectors[irq].prio = prio;\n+ } else {\n+ s->vectors[irq].prio = prio;\n+ }\n+\n+ trace_nvic_set_prio(irq, secure, prio);\n+}\n+\n+/* Return the current raw priority register value.\n+ * secure indicates the bank to use for banked exceptions (we assert if\n+ * we are passed secure=true for a non-banked exception).\n+ */\n+static int get_prio(NVICState *s, unsigned irq, bool secure)\n+{\n+ assert(irq > ARMV7M_EXCP_NMI); /* only use for configurable prios */\n+ assert(irq < s->num_irq);\n \n- trace_nvic_set_prio(irq, prio);\n+ if (secure) {\n+ assert(exc_is_banked(irq));\n+ return s->sec_vectors[irq].prio;\n+ } else {\n+ return s->vectors[irq].prio;\n+ }\n }\n \n /* Recompute state and assert irq line accordingly.\n@@ -1149,6 +1174,47 @@ static bool nvic_user_access_ok(NVICState *s, hwaddr offset, MemTxAttrs attrs)\n }\n }\n \n+static int shpr_bank(NVICState *s, int exc, MemTxAttrs attrs)\n+{\n+ /* Behaviour for the SHPR register field for this exception:\n+ * return M_REG_NS to use the nonsecure vector (including for\n+ * non-banked exceptions), M_REG_S for the secure version of\n+ * a banked exception, and -1 if this field should RAZ/WI.\n+ */\n+ switch (exc) {\n+ case ARMV7M_EXCP_MEM:\n+ case ARMV7M_EXCP_USAGE:\n+ case ARMV7M_EXCP_SVC:\n+ case ARMV7M_EXCP_PENDSV:\n+ case ARMV7M_EXCP_SYSTICK:\n+ /* Banked exceptions */\n+ return attrs.secure;\n+ case ARMV7M_EXCP_BUS:\n+ /* Not banked, RAZ/WI from nonsecure if BFHFNMINS is zero */\n+ if (!attrs.secure &&\n+ !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {\n+ return -1;\n+ }\n+ return M_REG_NS;\n+ case ARMV7M_EXCP_SECURE:\n+ /* Not banked, RAZ/WI from nonsecure */\n+ if (!attrs.secure) {\n+ return -1;\n+ }\n+ return M_REG_NS;\n+ case ARMV7M_EXCP_DEBUG:\n+ /* Not banked. TODO should RAZ/WI if DEMCR.SDME is set */\n+ return M_REG_NS;\n+ case 8 ... 10:\n+ case 13:\n+ /* RES0 */\n+ return -1;\n+ default:\n+ /* Not reachable due to decode of SHPR register addresses */\n+ g_assert_not_reached();\n+ }\n+}\n+\n static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,\n uint64_t *data, unsigned size,\n MemTxAttrs attrs)\n@@ -1213,10 +1279,16 @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,\n }\n }\n break;\n- case 0xd18 ... 0xd23: /* System Handler Priority. */\n+ case 0xd18 ... 0xd23: /* System Handler Priority (SHPR1, SHPR2, SHPR3) */\n val = 0;\n for (i = 0; i < size; i++) {\n- val |= s->vectors[(offset - 0xd14) + i].prio << (i * 8);\n+ unsigned hdlidx = (offset - 0xd14) + i;\n+ int sbank = shpr_bank(s, hdlidx, attrs);\n+\n+ if (sbank < 0) {\n+ continue;\n+ }\n+ val = deposit32(val, i * 8, 8, get_prio(s, hdlidx, sbank));\n }\n break;\n case 0xfe0 ... 0xfff: /* ID. */\n@@ -1299,15 +1371,21 @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,\n \n for (i = 0; i < size && startvec + i < s->num_irq; i++) {\n if (attrs.secure || s->itns[startvec + i]) {\n- set_prio(s, startvec + i, (value >> (i * 8)) & 0xff);\n+ set_prio(s, startvec + i, false, (value >> (i * 8)) & 0xff);\n }\n }\n nvic_irq_update(s);\n return MEMTX_OK;\n- case 0xd18 ... 0xd23: /* System Handler Priority. */\n+ case 0xd18 ... 0xd23: /* System Handler Priority (SHPR1, SHPR2, SHPR3) */\n for (i = 0; i < size; i++) {\n unsigned hdlidx = (offset - 0xd14) + i;\n- set_prio(s, hdlidx, (value >> (i * 8)) & 0xff);\n+ int newprio = extract32(value, i * 8, 8);\n+ int sbank = shpr_bank(s, hdlidx, attrs);\n+\n+ if (sbank < 0) {\n+ continue;\n+ }\n+ set_prio(s, hdlidx, sbank, newprio);\n }\n nvic_irq_update(s);\n return MEMTX_OK;\ndiff --git a/hw/intc/trace-events b/hw/intc/trace-events\nindex 94038b6..29bd308 100644\n--- a/hw/intc/trace-events\n+++ b/hw/intc/trace-events\n@@ -169,7 +169,7 @@ gicv3_redist_send_sgi(uint32_t cpu, int irq) \"GICv3 redistributor 0x%x pending S\n # hw/intc/armv7m_nvic.c\n nvic_recompute_state(int vectpending, int vectpending_prio, int exception_prio) \"NVIC state recomputed: vectpending %d vectpending_prio %d exception_prio %d\"\n nvic_recompute_state_secure(int vectpending, bool vectpending_is_s_banked, int vectpending_prio, int exception_prio) \"NVIC state recomputed: vectpending %d is_s_banked %d vectpending_prio %d exception_prio %d\"\n-nvic_set_prio(int irq, uint8_t prio) \"NVIC set irq %d priority %d\"\n+nvic_set_prio(int irq, bool secure, uint8_t prio) \"NVIC set irq %d secure-bank %d priority %d\"\n nvic_irq_update(int vectpending, int pendprio, int exception_prio, int level) \"NVIC vectpending %d pending prio %d exception_prio %d: setting irq line to %d\"\n nvic_escalate_prio(int irq, int irqprio, int runprio) \"NVIC escalating irq %d to HardFault: insufficient priority %d >= %d\"\n nvic_escalate_disabled(int irq) \"NVIC escalating irq %d to HardFault: disabled\"\n","prefixes":["10/19"]}