{"id":813002,"url":"http://patchwork.ozlabs.org/api/patches/813002/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-19-git-send-email-peter.maydell@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1505240046-11454-19-git-send-email-peter.maydell@linaro.org>","list_archive_url":null,"date":"2017-09-12T18:14:05","name":"[18/19] nvic: Make SHCSR banked for v8M","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"8b3f9e63fbe7af529d4de02bef85b9ff162b9f5f","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-19-git-send-email-peter.maydell@linaro.org/mbox/","series":[{"id":2751,"url":"http://patchwork.ozlabs.org/api/series/2751/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2751","date":"2017-09-12T18:13:53","name":"ARMv8M: support security extn in the NVIC","version":1,"mbox":"http://patchwork.ozlabs.org/series/2751/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/813002/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/813002/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xsCsg0Zvbz9s81\n\tfor ;\n\tWed, 13 Sep 2017 04:25:59 +1000 (AEST)","from localhost ([::1]:38011 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1drpsj-0006Ou-5U\n\tfor incoming@patchwork.ozlabs.org; Tue, 12 Sep 2017 14:25:57 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:43658)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1drph9-0003ba-H0\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 14:14:01 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1drph7-0006WS-Ky\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 14:13:59 -0400","from orth.archaic.org.uk ([2001:8b0:1d0::2]:37328)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1drph2-0006SF-SW; Tue, 12 Sep 2017 14:13:53 -0400","from pm215 by orth.archaic.org.uk with local (Exim 4.89)\n\t(envelope-from )\n\tid 1drph1-0001B2-S7; Tue, 12 Sep 2017 19:13:51 +0100"],"From":"Peter Maydell ","To":"qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org","Date":"Tue, 12 Sep 2017 19:14:05 +0100","Message-Id":"<1505240046-11454-19-git-send-email-peter.maydell@linaro.org>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1505240046-11454-1-git-send-email-peter.maydell@linaro.org>","References":"<1505240046-11454-1-git-send-email-peter.maydell@linaro.org>","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2001:8b0:1d0::2","Subject":"[Qemu-devel] [PATCH 18/19] nvic: Make SHCSR banked for v8M","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"patches@linaro.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"Handle banking of SHCSR: some register bits are banked between\nSecure and Non-Secure, and some are only accessible to Secure.\n\nSigned-off-by: Peter Maydell \n---\n hw/intc/armv7m_nvic.c | 221 ++++++++++++++++++++++++++++++++++++++------------\n 1 file changed, 169 insertions(+), 52 deletions(-)","diff":"diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c\nindex 21fd199..9613990 100644\n--- a/hw/intc/armv7m_nvic.c\n+++ b/hw/intc/armv7m_nvic.c\n@@ -770,50 +770,117 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)\n val = cpu->env.v7m.ccr[attrs.secure];\n val |= cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK;\n return val;\n- case 0xd24: /* System Handler Status. */\n+ case 0xd24: /* System Handler Control and State (SHCSR) */\n val = 0;\n- if (s->vectors[ARMV7M_EXCP_MEM].active) {\n- val |= (1 << 0);\n- }\n- if (s->vectors[ARMV7M_EXCP_BUS].active) {\n- val |= (1 << 1);\n- }\n- if (s->vectors[ARMV7M_EXCP_USAGE].active) {\n- val |= (1 << 3);\n+ if (attrs.secure) {\n+ if (s->sec_vectors[ARMV7M_EXCP_MEM].active) {\n+ val |= (1 << 0);\n+ }\n+ if (s->sec_vectors[ARMV7M_EXCP_HARD].active) {\n+ val |= (1 << 2);\n+ }\n+ if (s->sec_vectors[ARMV7M_EXCP_USAGE].active) {\n+ val |= (1 << 3);\n+ }\n+ if (s->sec_vectors[ARMV7M_EXCP_SVC].active) {\n+ val |= (1 << 7);\n+ }\n+ if (s->sec_vectors[ARMV7M_EXCP_PENDSV].active) {\n+ val |= (1 << 10);\n+ }\n+ if (s->sec_vectors[ARMV7M_EXCP_SYSTICK].active) {\n+ val |= (1 << 11);\n+ }\n+ if (s->sec_vectors[ARMV7M_EXCP_USAGE].pending) {\n+ val |= (1 << 12);\n+ }\n+ if (s->sec_vectors[ARMV7M_EXCP_MEM].pending) {\n+ val |= (1 << 13);\n+ }\n+ if (s->sec_vectors[ARMV7M_EXCP_SVC].pending) {\n+ val |= (1 << 15);\n+ }\n+ if (s->sec_vectors[ARMV7M_EXCP_MEM].enabled) {\n+ val |= (1 << 16);\n+ }\n+ if (s->sec_vectors[ARMV7M_EXCP_USAGE].enabled) {\n+ val |= (1 << 18);\n+ }\n+ if (s->sec_vectors[ARMV7M_EXCP_HARD].pending) {\n+ val |= (1 << 21);\n+ }\n+ /* SecureFault is not banked but is always RAZ/WI to NS */\n+ if (s->vectors[ARMV7M_EXCP_SECURE].active) {\n+ val |= (1 << 4);\n+ }\n+ if (s->vectors[ARMV7M_EXCP_SECURE].enabled) {\n+ val |= (1 << 19);\n+ }\n+ if (s->vectors[ARMV7M_EXCP_SECURE].pending) {\n+ val |= (1 << 20);\n+ }\n+ } else {\n+ if (s->vectors[ARMV7M_EXCP_MEM].active) {\n+ val |= (1 << 0);\n+ }\n+ if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {\n+ /* HARDFAULTACT, HARDFAULTPENDED not present in v7M */\n+ if (s->vectors[ARMV7M_EXCP_HARD].active) {\n+ val |= (1 << 2);\n+ }\n+ if (s->vectors[ARMV7M_EXCP_HARD].pending) {\n+ val |= (1 << 21);\n+ }\n+ }\n+ if (s->vectors[ARMV7M_EXCP_USAGE].active) {\n+ val |= (1 << 3);\n+ }\n+ if (s->vectors[ARMV7M_EXCP_SVC].active) {\n+ val |= (1 << 7);\n+ }\n+ if (s->vectors[ARMV7M_EXCP_PENDSV].active) {\n+ val |= (1 << 10);\n+ }\n+ if (s->vectors[ARMV7M_EXCP_SYSTICK].active) {\n+ val |= (1 << 11);\n+ }\n+ if (s->vectors[ARMV7M_EXCP_USAGE].pending) {\n+ val |= (1 << 12);\n+ }\n+ if (s->vectors[ARMV7M_EXCP_MEM].pending) {\n+ val |= (1 << 13);\n+ }\n+ if (s->vectors[ARMV7M_EXCP_SVC].pending) {\n+ val |= (1 << 15);\n+ }\n+ if (s->vectors[ARMV7M_EXCP_MEM].enabled) {\n+ val |= (1 << 16);\n+ }\n+ if (s->vectors[ARMV7M_EXCP_USAGE].enabled) {\n+ val |= (1 << 18);\n+ }\n }\n- if (s->vectors[ARMV7M_EXCP_SVC].active) {\n- val |= (1 << 7);\n+ if (attrs.secure || (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {\n+ if (s->vectors[ARMV7M_EXCP_BUS].active) {\n+ val |= (1 << 1);\n+ }\n+ if (s->vectors[ARMV7M_EXCP_BUS].pending) {\n+ val |= (1 << 14);\n+ }\n+ if (s->vectors[ARMV7M_EXCP_BUS].enabled) {\n+ val |= (1 << 17);\n+ }\n+ if (arm_feature(&cpu->env, ARM_FEATURE_V8) &&\n+ s->vectors[ARMV7M_EXCP_NMI].active) {\n+ /* NMIACT is not present in v7M */\n+ val |= (1 << 5);\n+ }\n }\n+\n+ /* TODO: this is RAZ/WI from NS if DEMCR.SDME is set */\n if (s->vectors[ARMV7M_EXCP_DEBUG].active) {\n val |= (1 << 8);\n }\n- if (s->vectors[ARMV7M_EXCP_PENDSV].active) {\n- val |= (1 << 10);\n- }\n- if (s->vectors[ARMV7M_EXCP_SYSTICK].active) {\n- val |= (1 << 11);\n- }\n- if (s->vectors[ARMV7M_EXCP_USAGE].pending) {\n- val |= (1 << 12);\n- }\n- if (s->vectors[ARMV7M_EXCP_MEM].pending) {\n- val |= (1 << 13);\n- }\n- if (s->vectors[ARMV7M_EXCP_BUS].pending) {\n- val |= (1 << 14);\n- }\n- if (s->vectors[ARMV7M_EXCP_SVC].pending) {\n- val |= (1 << 15);\n- }\n- if (s->vectors[ARMV7M_EXCP_MEM].enabled) {\n- val |= (1 << 16);\n- }\n- if (s->vectors[ARMV7M_EXCP_BUS].enabled) {\n- val |= (1 << 17);\n- }\n- if (s->vectors[ARMV7M_EXCP_USAGE].enabled) {\n- val |= (1 << 18);\n- }\n return val;\n case 0xd28: /* Configurable Fault Status. */\n /* The BFSR bits [15:8] are shared between security states\n@@ -1061,21 +1128,71 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,\n \n cpu->env.v7m.ccr[attrs.secure] = value;\n break;\n- case 0xd24: /* System Handler Control. */\n- s->vectors[ARMV7M_EXCP_MEM].active = (value & (1 << 0)) != 0;\n- s->vectors[ARMV7M_EXCP_BUS].active = (value & (1 << 1)) != 0;\n- s->vectors[ARMV7M_EXCP_USAGE].active = (value & (1 << 3)) != 0;\n- s->vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0;\n+ case 0xd24: /* System Handler Control and State (SHCSR) */\n+ if (attrs.secure) {\n+ s->sec_vectors[ARMV7M_EXCP_MEM].active = (value & (1 << 0)) != 0;\n+ /* Secure HardFault active bit cannot be written */\n+ s->sec_vectors[ARMV7M_EXCP_USAGE].active = (value & (1 << 3)) != 0;\n+ s->sec_vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0;\n+ s->sec_vectors[ARMV7M_EXCP_PENDSV].active =\n+ (value & (1 << 10)) != 0;\n+ s->sec_vectors[ARMV7M_EXCP_SYSTICK].active =\n+ (value & (1 << 11)) != 0;\n+ s->sec_vectors[ARMV7M_EXCP_USAGE].pending =\n+ (value & (1 << 12)) != 0;\n+ s->sec_vectors[ARMV7M_EXCP_MEM].pending = (value & (1 << 13)) != 0;\n+ s->sec_vectors[ARMV7M_EXCP_SVC].pending = (value & (1 << 15)) != 0;\n+ s->sec_vectors[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0;\n+ s->sec_vectors[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0;\n+ s->sec_vectors[ARMV7M_EXCP_USAGE].enabled =\n+ (value & (1 << 18)) != 0;\n+ /* SecureFault not banked, but RAZ/WI to NS */\n+ s->vectors[ARMV7M_EXCP_SECURE].active = (value & (1 << 4)) != 0;\n+ s->vectors[ARMV7M_EXCP_SECURE].enabled = (value & (1 << 19)) != 0;\n+ s->vectors[ARMV7M_EXCP_SECURE].pending = (value & (1 << 20)) != 0;\n+ } else {\n+ s->vectors[ARMV7M_EXCP_MEM].active = (value & (1 << 0)) != 0;\n+ if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {\n+ /* HARDFAULTPENDED is not present in v7M */\n+ s->vectors[ARMV7M_EXCP_HARD].pending = (value & (1 << 21)) != 0;\n+ }\n+ s->vectors[ARMV7M_EXCP_USAGE].active = (value & (1 << 3)) != 0;\n+ s->vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0;\n+ s->vectors[ARMV7M_EXCP_PENDSV].active = (value & (1 << 10)) != 0;\n+ s->vectors[ARMV7M_EXCP_SYSTICK].active = (value & (1 << 11)) != 0;\n+ s->vectors[ARMV7M_EXCP_USAGE].pending = (value & (1 << 12)) != 0;\n+ s->vectors[ARMV7M_EXCP_MEM].pending = (value & (1 << 13)) != 0;\n+ s->vectors[ARMV7M_EXCP_SVC].pending = (value & (1 << 15)) != 0;\n+ s->vectors[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0;\n+ s->vectors[ARMV7M_EXCP_USAGE].enabled = (value & (1 << 18)) != 0;\n+ }\n+ if (attrs.secure || (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {\n+ s->vectors[ARMV7M_EXCP_BUS].active = (value & (1 << 1)) != 0;\n+ s->vectors[ARMV7M_EXCP_BUS].pending = (value & (1 << 14)) != 0;\n+ s->vectors[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0;\n+ }\n+ /* NMIACT can only be written if the write is of a zero, with\n+ * BFHFNMINS 1, and by the CPU in secure state via the NS alias.\n+ */\n+ if (!attrs.secure && cpu->env.v7m.secure &&\n+ (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) &&\n+ (value & (1 << 5)) == 0) {\n+ s->vectors[ARMV7M_EXCP_NMI].active = 0;\n+ }\n+ /* HARDFAULTACT can only be written if the write is of a zero\n+ * to the non-secure HardFault state by the CPU in secure state.\n+ * The only case where we can be targeting the non-secure HF state\n+ * when in secure state is if this is a write via the NS alias\n+ * and BFHFNMINS is 1.\n+ */\n+ if (!attrs.secure && cpu->env.v7m.secure &&\n+ (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) &&\n+ (value & (1 << 2)) == 0) {\n+ s->vectors[ARMV7M_EXCP_HARD].active = 0;\n+ }\n+\n+ /* TODO: this is RAZ/WI from NS if DEMCR.SDME is set */\n s->vectors[ARMV7M_EXCP_DEBUG].active = (value & (1 << 8)) != 0;\n- s->vectors[ARMV7M_EXCP_PENDSV].active = (value & (1 << 10)) != 0;\n- s->vectors[ARMV7M_EXCP_SYSTICK].active = (value & (1 << 11)) != 0;\n- s->vectors[ARMV7M_EXCP_USAGE].pending = (value & (1 << 12)) != 0;\n- s->vectors[ARMV7M_EXCP_MEM].pending = (value & (1 << 13)) != 0;\n- s->vectors[ARMV7M_EXCP_BUS].pending = (value & (1 << 14)) != 0;\n- s->vectors[ARMV7M_EXCP_SVC].pending = (value & (1 << 15)) != 0;\n- s->vectors[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0;\n- s->vectors[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0;\n- s->vectors[ARMV7M_EXCP_USAGE].enabled = (value & (1 << 18)) != 0;\n nvic_irq_update(s);\n break;\n case 0xd28: /* Configurable Fault Status. */\n","prefixes":["18/19"]}