{"id":812994,"url":"http://patchwork.ozlabs.org/api/patches/812994/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-17-git-send-email-peter.maydell@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1505240046-11454-17-git-send-email-peter.maydell@linaro.org>","list_archive_url":null,"date":"2017-09-12T18:14:03","name":"[16/19] target/arm: Handle banking in negative-execution-priority check in cpu_mmu_index()","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"ce4d30b3dffb1798dfba3b47bede6a5571954a67","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-17-git-send-email-peter.maydell@linaro.org/mbox/","series":[{"id":2751,"url":"http://patchwork.ozlabs.org/api/series/2751/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2751","date":"2017-09-12T18:13:53","name":"ARMv8M: support security extn in the NVIC","version":1,"mbox":"http://patchwork.ozlabs.org/series/2751/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/812994/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/812994/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xsClZ4C0lz9s3T\n\tfor ;\n\tWed, 13 Sep 2017 04:20:42 +1000 (AEST)","from localhost ([::1]:37976 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1drpnc-0000jl-Gv\n\tfor incoming@patchwork.ozlabs.org; Tue, 12 Sep 2017 14:20:40 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:43572)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1drph6-0003Wv-4D\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 14:13:57 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1drph4-0006Ue-Ro\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 14:13:56 -0400","from orth.archaic.org.uk ([2001:8b0:1d0::2]:37324)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1drph1-0006R3-Cj; Tue, 12 Sep 2017 14:13:51 -0400","from pm215 by orth.archaic.org.uk with local (Exim 4.89)\n\t(envelope-from )\n\tid 1drph0-0001A4-BP; Tue, 12 Sep 2017 19:13:50 +0100"],"From":"Peter Maydell ","To":"qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org","Date":"Tue, 12 Sep 2017 19:14:03 +0100","Message-Id":"<1505240046-11454-17-git-send-email-peter.maydell@linaro.org>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1505240046-11454-1-git-send-email-peter.maydell@linaro.org>","References":"<1505240046-11454-1-git-send-email-peter.maydell@linaro.org>","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2001:8b0:1d0::2","Subject":"[Qemu-devel] [PATCH 16/19] target/arm: Handle banking in\n\tnegative-execution-priority check in cpu_mmu_index()","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"patches@linaro.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"Now that we have a banked FAULTMASK register and banked exceptions,\nwe can implement the correct check in cpu_mmu_index() for whether\nthe MPU_CTRL.HFNMIENA bit's effect should apply. This bit causes\nhandlers which have requested a negative execution priority to run\nwith the MPU disabled. In v8M the test has to check this for the\ncurrent security state and so takes account of banking.\n\nSigned-off-by: Peter Maydell \n---\n target/arm/cpu.h | 21 ++++++++++++++++-----\n hw/intc/armv7m_nvic.c | 29 +++++++++++++++++++++++++++++\n 2 files changed, 45 insertions(+), 5 deletions(-)","diff":"diff --git a/target/arm/cpu.h b/target/arm/cpu.h\nindex 7a93354..02be3ca 100644\n--- a/target/arm/cpu.h\n+++ b/target/arm/cpu.h\n@@ -1498,6 +1498,21 @@ int armv7m_nvic_complete_irq(void *opaque, int irq);\n * (v8M ARM ARM I_PKLD.)\n */\n int armv7m_nvic_raw_execution_priority(void *opaque);\n+/**\n+ * armv7m_nvic_neg_prio_requested: return true if the requested execution\n+ * priority is negative for the specified security state.\n+ * @opaque: the NVIC\n+ * @secure: the security state to test\n+ * This corresponds to the pseudocode IsReqExecPriNeg().\n+ */\n+#ifndef CONFIG_USER_ONLY\n+bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure);\n+#else\n+static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)\n+{\n+ return false;\n+}\n+#endif\n \n /* Interface for defining coprocessor registers.\n * Registers are defined in tables of arm_cp_reginfo structs\n@@ -2280,11 +2295,7 @@ static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)\n if (arm_feature(env, ARM_FEATURE_M)) {\n ARMMMUIdx mmu_idx = el == 0 ? ARMMMUIdx_MUser : ARMMMUIdx_MPriv;\n \n- /* Execution priority is negative if FAULTMASK is set or\n- * we're in a HardFault or NMI handler.\n- */\n- if ((env->v7m.exception > 0 && env->v7m.exception <= 3)\n- || env->v7m.faultmask[env->v7m.secure]) {\n+ if (armv7m_nvic_neg_prio_requested(env->nvic, env->v7m.secure)) {\n mmu_idx = ARMMMUIdx_MNegPri;\n }\n \ndiff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c\nindex b13327d..5e5aecd 100644\n--- a/hw/intc/armv7m_nvic.c\n+++ b/hw/intc/armv7m_nvic.c\n@@ -368,6 +368,35 @@ static inline int nvic_exec_prio(NVICState *s)\n return MIN(running, s->exception_prio);\n }\n \n+bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)\n+{\n+ /* Return true if the requested execution priority is negative\n+ * for the specified security state, ie that security state\n+ * has an active NMI or HardFault or has set its FAULTMASK.\n+ * Note that this is not the same as whether the execution\n+ * priority is actually negative (for instance AIRCR.PRIS may\n+ * mean we don't allow FAULTMASK_NS to actually make the execution\n+ * priority negative). Compare pseudocode IsReqExcPriNeg().\n+ */\n+ NVICState *s = opaque;\n+\n+ if (s->cpu->env.v7m.faultmask[secure]) {\n+ return true;\n+ }\n+\n+ if (secure ? s->sec_vectors[ARMV7M_EXCP_HARD].active :\n+ s->vectors[ARMV7M_EXCP_HARD].active) {\n+ return true;\n+ }\n+\n+ if (s->vectors[ARMV7M_EXCP_NMI].active &&\n+ exc_targets_secure(s, ARMV7M_EXCP_NMI) == secure) {\n+ return true;\n+ }\n+\n+ return false;\n+}\n+\n bool armv7m_nvic_can_take_pending_exception(void *opaque)\n {\n NVICState *s = opaque;\n","prefixes":["16/19"]}