{"id":812990,"url":"http://patchwork.ozlabs.org/api/patches/812990/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-5-git-send-email-peter.maydell@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1505240046-11454-5-git-send-email-peter.maydell@linaro.org>","list_archive_url":null,"date":"2017-09-12T18:13:51","name":"[04/19] nvic: Add cached vectpending_prio state","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"d00e52d3b52c0a080e8bb55fd2c79e4dd2a33c96","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-5-git-send-email-peter.maydell@linaro.org/mbox/","series":[{"id":2751,"url":"http://patchwork.ozlabs.org/api/series/2751/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2751","date":"2017-09-12T18:13:53","name":"ARMv8M: support security extn in the NVIC","version":1,"mbox":"http://patchwork.ozlabs.org/series/2751/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/812990/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/812990/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xsCgb2Mdhz9sNV\n\tfor ;\n\tWed, 13 Sep 2017 04:17:15 +1000 (AEST)","from localhost ([::1]:37959 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1drpkH-0005t3-CD\n\tfor incoming@patchwork.ozlabs.org; Tue, 12 Sep 2017 14:17:13 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:43258)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1drpgx-0003Mw-Or\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 14:13:50 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1drpgw-0006NR-9A\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 14:13:47 -0400","from orth.archaic.org.uk ([2001:8b0:1d0::2]:37288)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1drpgt-0006Js-5P; Tue, 12 Sep 2017 14:13:43 -0400","from pm215 by orth.archaic.org.uk with local (Exim 4.89)\n\t(envelope-from )\n\tid 1drpgs-000141-6X; Tue, 12 Sep 2017 19:13:42 +0100"],"From":"Peter Maydell ","To":"qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org","Date":"Tue, 12 Sep 2017 19:13:51 +0100","Message-Id":"<1505240046-11454-5-git-send-email-peter.maydell@linaro.org>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1505240046-11454-1-git-send-email-peter.maydell@linaro.org>","References":"<1505240046-11454-1-git-send-email-peter.maydell@linaro.org>","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2001:8b0:1d0::2","Subject":"[Qemu-devel] [PATCH 04/19] nvic: Add cached vectpending_prio state","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"patches@linaro.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"Instead of looking up the pending priority\nin nvic_pending_prio(), cache it in a new state struct\nfield. The calculation of the pending priority given\nthe interrupt number is more complicated in v8M with\nthe security extension, so the caching will be worthwhile.\n\nThis changes nvic_pending_prio() from returning a full\n(group + subpriority) priority value to returning a group\npriority. This doesn't require changes to its callsites\nbecause we use it only in comparisons of the form\n execution_prio > nvic_pending_prio()\nand execution priority is always a group priority, so\na test (exec prio > full prio) is true if and only if\n(execprio > group_prio).\n\n(Architecturally the expected comparison is with the\ngroup priority for this sort of \"would we preempt\" test;\nwe were only doing a test with a full priority as an\noptimisation to avoid the mask, which is possible\nprecisely because the two comparisons always give the\nsame answer.)\n\nSigned-off-by: Peter Maydell \n---\n include/hw/intc/armv7m_nvic.h | 2 ++\n hw/intc/armv7m_nvic.c | 23 +++++++++++++----------\n hw/intc/trace-events | 2 +-\n 3 files changed, 16 insertions(+), 11 deletions(-)","diff":"diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h\nindex 87c78b3..329774e 100644\n--- a/include/hw/intc/armv7m_nvic.h\n+++ b/include/hw/intc/armv7m_nvic.h\n@@ -62,6 +62,7 @@ typedef struct NVICState {\n * - vectpending\n * - vectpending_is_secure\n * - exception_prio\n+ * - vectpending_prio\n */\n unsigned int vectpending; /* highest prio pending enabled exception */\n /* true if vectpending is a banked secure exception, ie it is in\n@@ -69,6 +70,7 @@ typedef struct NVICState {\n */\n bool vectpending_is_s_banked;\n int exception_prio; /* group prio of the highest prio active exception */\n+ int vectpending_prio; /* group prio of the exeception in vectpending */\n \n MemoryRegion sysregmem;\n MemoryRegion sysreg_ns_mem;\ndiff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c\nindex 417a456..8388d64 100644\n--- a/hw/intc/armv7m_nvic.c\n+++ b/hw/intc/armv7m_nvic.c\n@@ -61,10 +61,10 @@ static const uint8_t nvic_id[] = {\n \n static int nvic_pending_prio(NVICState *s)\n {\n- /* return the priority of the current pending interrupt,\n+ /* return the group priority of the current pending interrupt,\n * or NVIC_NOEXC_PRIO if no interrupt is pending\n */\n- return s->vectpending ? s->vectors[s->vectpending].prio : NVIC_NOEXC_PRIO;\n+ return s->vectpending_prio;\n }\n \n /* Return the value of the ISCR RETTOBASE bit:\n@@ -156,10 +156,17 @@ static void nvic_recompute_state(NVICState *s)\n active_prio &= nvic_gprio_mask(s);\n }\n \n+ if (pend_prio > 0) {\n+ pend_prio &= nvic_gprio_mask(s);\n+ }\n+\n s->vectpending = pend_irq;\n+ s->vectpending_prio = pend_prio;\n s->exception_prio = active_prio;\n \n- trace_nvic_recompute_state(s->vectpending, s->exception_prio);\n+ trace_nvic_recompute_state(s->vectpending,\n+ s->vectpending_prio,\n+ s->exception_prio);\n }\n \n /* Return the current execution priority of the CPU\n@@ -323,7 +330,6 @@ void armv7m_nvic_acknowledge_irq(void *opaque)\n CPUARMState *env = &s->cpu->env;\n const int pending = s->vectpending;\n const int running = nvic_exec_prio(s);\n- int pendgroupprio;\n VecInfo *vec;\n \n assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq);\n@@ -333,13 +339,9 @@ void armv7m_nvic_acknowledge_irq(void *opaque)\n assert(vec->enabled);\n assert(vec->pending);\n \n- pendgroupprio = vec->prio;\n- if (pendgroupprio > 0) {\n- pendgroupprio &= nvic_gprio_mask(s);\n- }\n- assert(pendgroupprio < running);\n+ assert(s->vectpending_prio < running);\n \n- trace_nvic_acknowledge_irq(pending, vec->prio);\n+ trace_nvic_acknowledge_irq(pending, s->vectpending_prio);\n \n vec->active = 1;\n vec->pending = 0;\n@@ -1251,6 +1253,7 @@ static void armv7m_nvic_reset(DeviceState *dev)\n s->exception_prio = NVIC_NOEXC_PRIO;\n s->vectpending = 0;\n s->vectpending_is_s_banked = false;\n+ s->vectpending_prio = NVIC_NOEXC_PRIO;\n }\n \n static void nvic_systick_trigger(void *opaque, int n, int level)\ndiff --git a/hw/intc/trace-events b/hw/intc/trace-events\nindex 4762329..5635a5f 100644\n--- a/hw/intc/trace-events\n+++ b/hw/intc/trace-events\n@@ -167,7 +167,7 @@ gicv3_redist_set_irq(uint32_t cpu, int irq, int level) \"GICv3 redistributor 0x%x\n gicv3_redist_send_sgi(uint32_t cpu, int irq) \"GICv3 redistributor 0x%x pending SGI %d\"\n \n # hw/intc/armv7m_nvic.c\n-nvic_recompute_state(int vectpending, int exception_prio) \"NVIC state recomputed: vectpending %d exception_prio %d\"\n+nvic_recompute_state(int vectpending, int vectpending_prio, int exception_prio) \"NVIC state recomputed: vectpending %d vectpending_prio %d exception_prio %d\"\n nvic_set_prio(int irq, uint8_t prio) \"NVIC set irq %d priority %d\"\n nvic_irq_update(int vectpending, int pendprio, int exception_prio, int level) \"NVIC vectpending %d pending prio %d exception_prio %d: setting irq line to %d\"\n nvic_escalate_prio(int irq, int irqprio, int runprio) \"NVIC escalating irq %d to HardFault: insufficient priority %d >= %d\"\n","prefixes":["04/19"]}