{"id":812989,"url":"http://patchwork.ozlabs.org/api/patches/812989/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/patch/f9eac5a4-0567-4da8-8eb7-803a5d6e8324@foss.arm.com/","project":{"id":17,"url":"http://patchwork.ozlabs.org/api/projects/17/?format=json","name":"GNU Compiler Collection","link_name":"gcc","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"","list_archive_url":null,"date":"2017-09-12T18:15:29","name":"[AArch64] Refactor of aarch64-ldpstp.md","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"a260ae941bef7aa3f5113e3b7fb2f38c7116a7ea","submitter":{"id":71950,"url":"http://patchwork.ozlabs.org/api/people/71950/?format=json","name":"Jackson Woodruff","email":"jackson.woodruff@foss.arm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/gcc/patch/f9eac5a4-0567-4da8-8eb7-803a5d6e8324@foss.arm.com/mbox/","series":[{"id":2753,"url":"http://patchwork.ozlabs.org/api/series/2753/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/list/?series=2753","date":"2017-09-12T18:15:29","name":"[AArch64] Refactor of aarch64-ldpstp.md","version":1,"mbox":"http://patchwork.ozlabs.org/series/2753/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/812989/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/812989/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list gcc-patches@gcc.gnu.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; 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Tue, 12 Sep 2017 11:15:32 -0700 (PDT)","from [10.2.206.195] (e112997-lin.cambridge.arm.com\n\t[10.2.206.195])\tby usa-sjc-imap-foss1.foss.arm.com (Postfix)\n\twith ESMTPSA id 88CA13F578; Tue, 12 Sep 2017 11:15:31 -0700 (PDT)"],"DomainKey-Signature":"a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender:to\n\t:from:subject:message-id:date:mime-version:content-type; q=dns;\n\ts=default; b=LK/dr4E+Sfcg6nxRkGFWoW1SM0HtIks8DC3KXueLDYPMWiTDTS\n\tfiaAxZ8FmWkbpUC2mMWA1KIXMPzxcKCMUwfJQgp/nhxpUjkMnRfePv5RcgXkqg4v\n\tuJDGizqJ8CknmcQVpoyWMK77Gg0O1Xd1rk6o/Qk9qX9CCOCW1DBBKiYt4=","DKIM-Signature":"v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender:to\n\t:from:subject:message-id:date:mime-version:content-type; s=\n\tdefault; bh=A4/X/R34MsMH3fMek7SE8GcEUYs=; b=Gm5eJ4MtHSHFLV9KHv7m\n\taaHLX8K9T4NqtDtL7Ka4o5E4LGEQRaTSRwj4R3pyoiL8dac95qf/QkFkNrUQaQrB\n\t4hSBDbgUgJnOHBdHOCgtOh7NcCINAjEJ3XGbC2c6XMDFlmQrWmBE8efcV96MeqG5\n\tjN3PE3KSRzaKvoh6GeSJneQ=","Mailing-List":"contact gcc-patches-help@gcc.gnu.org; run by ezmlm","Precedence":"bulk","List-Id":"","List-Unsubscribe":"","List-Archive":"","List-Post":"","List-Help":"","Sender":"gcc-patches-owner@gcc.gnu.org","X-Virus-Found":"No","X-Spam-SWARE-Status":"No, score=-20.5 required=5.0 tests=BAYES_00, GIT_PATCH_0,\n\tGIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3,\n\tKAM_LAZY_DOMAIN_SECURITY, KAM_LOTSOFHASH, MEDICAL_SUBJECT,\n\tRP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=H*MI:0567,\n\tH*M:0567","X-HELO":"foss.arm.com","To":"GCC Patches ,\n\tJames Greenhalgh ,\n\tRichard Earnshaw ","From":"Jackson Woodruff ","Subject":"[AArch64, patch] Refactor of aarch64-ldpstp.md","Message-ID":"","Date":"Tue, 12 Sep 2017 19:15:29 +0100","User-Agent":"Mozilla/5.0 (X11; Linux x86_64;\n\trv:52.0) Gecko/20100101 Thunderbird/52.3.0","MIME-Version":"1.0","Content-Type":"multipart/mixed;\n\tboundary=\"------------134780F49C6C1FDE1FFA2E54\"","X-IsSubscribed":"yes"},"content":"Hi all,\n\nThis patch removes a lot of duplicated code in aarch64-ldpstp.md.\n\nThe patterns that did not previously generate a base register now\ndo not check for aarch64_mem_pair_operand in the pattern. This has\nbeen extracted to a check in aarch64_operands_ok_for_ldpstp.\n\nAll patterns in the file used to have explicit switching code to\nswap loads and stores that were in the wrong order.\n\nThis has been extracted into aarch64_ldp_str_operands\nand aarch64_gen_adjusted_ldp_stp.\n\nThis patch is based on my patch here: \nhttps://gcc.gnu.org/ml/gcc-patches/2017-09/msg00346.html so should go in \nafter it.\n\n\nBootstrap and regtest OK on AArch64.\n\nOK for trunk?\n\nJackson.\n\ngcc/\n\n2017-09-07 Jackson Woodruff \n\n\t* config/aarch64/aarch64-ldpstp.md: Replace uses of\n\taarch64_mem_pair_operand with memory_operand and delete\n\toperand swapping code.\n\t* config/aarch64/aarch64.c (aarch64_operands_ok_for_ldpstp):\n\tAdd check for legitimate_address.\n\t(aarch64_gen_adjusted_ldpstp): Add swap.\n\t(aarch64_swap_ldrstr_operands): New.\n\t* config/aarch64/aarch64-protos.h: Add\n\taarch64_swap_ldrstr_operands.","diff":"diff --git a/gcc/config/aarch64/aarch64-ldpstp.md b/gcc/config/aarch64/aarch64-ldpstp.md\nindex 14e860d258e548d4118d957675f8bdbb74615337..126bb702f6399d13ab2dc6c8b99bcbbf3b3a7516 100644\n--- a/gcc/config/aarch64/aarch64-ldpstp.md\n+++ b/gcc/config/aarch64/aarch64-ldpstp.md\n@@ -20,26 +20,18 @@\n \n (define_peephole2\n [(set (match_operand:GPI 0 \"register_operand\" \"\")\n-\t(match_operand:GPI 1 \"aarch64_mem_pair_operand\" \"\"))\n+\t(match_operand:GPI 1 \"memory_operand\" \"\"))\n (set (match_operand:GPI 2 \"register_operand\" \"\")\n \t(match_operand:GPI 3 \"memory_operand\" \"\"))]\n \"aarch64_operands_ok_for_ldpstp (operands, true, mode)\"\n [(parallel [(set (match_dup 0) (match_dup 1))\n \t (set (match_dup 2) (match_dup 3))])]\n {\n- rtx base, offset_1, offset_2;\n-\n- extract_base_offset_in_addr (operands[1], &base, &offset_1);\n- extract_base_offset_in_addr (operands[3], &base, &offset_2);\n- if (INTVAL (offset_1) > INTVAL (offset_2))\n- {\n- std::swap (operands[0], operands[2]);\n- std::swap (operands[1], operands[3]);\n- }\n+ aarch64_swap_ldrstr_operands (operands, 1);\n })\n \n (define_peephole2\n- [(set (match_operand:GPI 0 \"aarch64_mem_pair_operand\" \"\")\n+ [(set (match_operand:GPI 0 \"memory_operand\" \"\")\n \t(match_operand:GPI 1 \"aarch64_reg_or_zero\" \"\"))\n (set (match_operand:GPI 2 \"memory_operand\" \"\")\n \t(match_operand:GPI 3 \"aarch64_reg_or_zero\" \"\"))]\n@@ -47,39 +39,23 @@\n [(parallel [(set (match_dup 0) (match_dup 1))\n \t (set (match_dup 2) (match_dup 3))])]\n {\n- rtx base, offset_1, offset_2;\n-\n- extract_base_offset_in_addr (operands[0], &base, &offset_1);\n- extract_base_offset_in_addr (operands[2], &base, &offset_2);\n- if (INTVAL (offset_1) > INTVAL (offset_2))\n- {\n- std::swap (operands[0], operands[2]);\n- std::swap (operands[1], operands[3]);\n- }\n+ aarch64_swap_ldrstr_operands (operands, 0);\n })\n \n (define_peephole2\n [(set (match_operand:GPF 0 \"register_operand\" \"\")\n-\t(match_operand:GPF 1 \"aarch64_mem_pair_operand\" \"\"))\n+\t(match_operand:GPF 1 \"memory_operand\" \"\"))\n (set (match_operand:GPF 2 \"register_operand\" \"\")\n \t(match_operand:GPF 3 \"memory_operand\" \"\"))]\n \"aarch64_operands_ok_for_ldpstp (operands, true, mode)\"\n [(parallel [(set (match_dup 0) (match_dup 1))\n \t (set (match_dup 2) (match_dup 3))])]\n {\n- rtx base, offset_1, offset_2;\n-\n- extract_base_offset_in_addr (operands[1], &base, &offset_1);\n- extract_base_offset_in_addr (operands[3], &base, &offset_2);\n- if (INTVAL (offset_1) > INTVAL (offset_2))\n- {\n- std::swap (operands[0], operands[2]);\n- std::swap (operands[1], operands[3]);\n- }\n+ aarch64_swap_ldrstr_operands (operands, 1);\n })\n \n (define_peephole2\n- [(set (match_operand:GPF 0 \"aarch64_mem_pair_operand\" \"\")\n+ [(set (match_operand:GPF 0 \"memory_operand\" \"\")\n \t(match_operand:GPF 1 \"aarch64_reg_or_fp_zero\" \"\"))\n (set (match_operand:GPF 2 \"memory_operand\" \"\")\n \t(match_operand:GPF 3 \"aarch64_reg_or_fp_zero\" \"\"))]\n@@ -87,39 +63,23 @@\n [(parallel [(set (match_dup 0) (match_dup 1))\n \t (set (match_dup 2) (match_dup 3))])]\n {\n- rtx base, offset_1, offset_2;\n-\n- extract_base_offset_in_addr (operands[0], &base, &offset_1);\n- extract_base_offset_in_addr (operands[2], &base, &offset_2);\n- if (INTVAL (offset_1) > INTVAL (offset_2))\n- {\n- std::swap (operands[0], operands[2]);\n- std::swap (operands[1], operands[3]);\n- }\n+ aarch64_swap_ldrstr_operands (operands, 0);\n })\n \n (define_peephole2\n [(set (match_operand:DREG 0 \"register_operand\" \"\")\n-\t(match_operand:DREG 1 \"aarch64_mem_pair_operand\" \"\"))\n+\t(match_operand:DREG 1 \"memory_operand\" \"\"))\n (set (match_operand:DREG2 2 \"register_operand\" \"\")\n \t(match_operand:DREG2 3 \"memory_operand\" \"\"))]\n \"aarch64_operands_ok_for_ldpstp (operands, true, mode)\"\n [(parallel [(set (match_dup 0) (match_dup 1))\n \t (set (match_dup 2) (match_dup 3))])]\n {\n- rtx base, offset_1, offset_2;\n-\n- extract_base_offset_in_addr (operands[1], &base, &offset_1);\n- extract_base_offset_in_addr (operands[3], &base, &offset_2);\n- if (INTVAL (offset_1) > INTVAL (offset_2))\n- {\n- std::swap (operands[0], operands[2]);\n- std::swap (operands[1], operands[3]);\n- }\n+ aarch64_swap_ldrstr_operands (operands, 1);\n })\n \n (define_peephole2\n- [(set (match_operand:DREG 0 \"aarch64_mem_pair_operand\" \"\")\n+ [(set (match_operand:DREG 0 \"memory_operand\" \"\")\n \t(match_operand:DREG 1 \"register_operand\" \"\"))\n (set (match_operand:DREG2 2 \"memory_operand\" \"\")\n \t(match_operand:DREG2 3 \"register_operand\" \"\"))]\n@@ -128,57 +88,33 @@\n [(parallel [(set (match_dup 0) (match_dup 1))\n \t (set (match_dup 2) (match_dup 3))])]\n {\n- rtx base, offset_1, offset_2;\n-\n- extract_base_offset_in_addr (operands[0], &base, &offset_1);\n- extract_base_offset_in_addr (operands[2], &base, &offset_2);\n- if (INTVAL (offset_1) > INTVAL (offset_2))\n- {\n- std::swap (operands[0], operands[2]);\n- std::swap (operands[1], operands[3]);\n- }\n+ aarch64_swap_ldrstr_operands (operands, 0);\n })\n \n ;; Handle sign/zero extended consecutive load/store.\n \n (define_peephole2\n [(set (match_operand:DI 0 \"register_operand\" \"\")\n-\t(sign_extend:DI (match_operand:SI 1 \"aarch64_mem_pair_operand\" \"\")))\n+\t(sign_extend:DI (match_operand:SI 1 \"memory_operand\" \"\")))\n (set (match_operand:DI 2 \"register_operand\" \"\")\n \t(sign_extend:DI (match_operand:SI 3 \"memory_operand\" \"\")))]\n \"aarch64_operands_ok_for_ldpstp (operands, true, SImode)\"\n [(parallel [(set (match_dup 0) (sign_extend:DI (match_dup 1)))\n \t (set (match_dup 2) (sign_extend:DI (match_dup 3)))])]\n {\n- rtx base, offset_1, offset_2;\n-\n- extract_base_offset_in_addr (operands[1], &base, &offset_1);\n- extract_base_offset_in_addr (operands[3], &base, &offset_2);\n- if (INTVAL (offset_1) > INTVAL (offset_2))\n- {\n- std::swap (operands[0], operands[2]);\n- std::swap (operands[1], operands[3]);\n- }\n+ aarch64_swap_ldrstr_operands (operands, 1);\n })\n \n (define_peephole2\n [(set (match_operand:DI 0 \"register_operand\" \"\")\n-\t(zero_extend:DI (match_operand:SI 1 \"aarch64_mem_pair_operand\" \"\")))\n+\t(zero_extend:DI (match_operand:SI 1 \"memory_operand\" \"\")))\n (set (match_operand:DI 2 \"register_operand\" \"\")\n \t(zero_extend:DI (match_operand:SI 3 \"memory_operand\" \"\")))]\n \"aarch64_operands_ok_for_ldpstp (operands, true, SImode)\"\n [(parallel [(set (match_dup 0) (zero_extend:DI (match_dup 1)))\n \t (set (match_dup 2) (zero_extend:DI (match_dup 3)))])]\n {\n- rtx base, offset_1, offset_2;\n-\n- extract_base_offset_in_addr (operands[1], &base, &offset_1);\n- extract_base_offset_in_addr (operands[3], &base, &offset_2);\n- if (INTVAL (offset_1) > INTVAL (offset_2))\n- {\n- std::swap (operands[0], operands[2]);\n- std::swap (operands[1], operands[3]);\n- }\n+ aarch64_swap_ldrstr_operands (operands, 1);\n })\n \n ;; Handle storing of a floating point zero.\n@@ -186,7 +122,7 @@\n ;; as aarch64_operands_ok_for_ldpstp checks that the modes are\n ;; compatible.\n (define_peephole2\n- [(set (match_operand:DSX 0 \"aarch64_mem_pair_operand\" \"\")\n+ [(set (match_operand:DSX 0 \"memory_operand\" \"\")\n \t(match_operand:DSX 1 \"aarch64_reg_zero_or_fp_zero\" \"\"))\n (set (match_operand: 2 \"memory_operand\" \"\")\n \t(match_operand: 3 \"aarch64_reg_zero_or_fp_zero\" \"\"))]\n@@ -224,18 +160,6 @@\n \"aarch64_operands_adjust_ok_for_ldpstp (operands, true, mode)\"\n [(const_int 0)]\n {\n- rtx base, offset_1, offset_2;\n-\n- extract_base_offset_in_addr (operands[1], &base, &offset_1);\n- extract_base_offset_in_addr (operands[3], &base, &offset_2);\n- if (INTVAL (offset_1) > INTVAL (offset_2))\n- {\n- std::swap (operands[0], operands[6]);\n- std::swap (operands[1], operands[7]);\n- std::swap (operands[2], operands[4]);\n- std::swap (operands[3], operands[5]);\n- }\n-\n if (aarch64_gen_adjusted_ldpstp (operands, true, mode, UNKNOWN))\n DONE;\n else\n@@ -256,18 +180,6 @@\n \"aarch64_operands_adjust_ok_for_ldpstp (operands, true, mode)\"\n [(const_int 0)]\n {\n- rtx base, offset_1, offset_2;\n-\n- extract_base_offset_in_addr (operands[1], &base, &offset_1);\n- extract_base_offset_in_addr (operands[3], &base, &offset_2);\n- if (INTVAL (offset_1) > INTVAL (offset_2))\n- {\n- std::swap (operands[0], operands[6]);\n- std::swap (operands[1], operands[7]);\n- std::swap (operands[2], operands[4]);\n- std::swap (operands[3], operands[5]);\n- }\n-\n if (aarch64_gen_adjusted_ldpstp (operands, true, mode, UNKNOWN))\n DONE;\n else\n@@ -288,18 +200,6 @@\n \"aarch64_operands_adjust_ok_for_ldpstp (operands, true, SImode)\"\n [(const_int 0)]\n {\n- rtx base, offset_1, offset_2;\n-\n- extract_base_offset_in_addr (operands[1], &base, &offset_1);\n- extract_base_offset_in_addr (operands[3], &base, &offset_2);\n- if (INTVAL (offset_1) > INTVAL (offset_2))\n- {\n- std::swap (operands[0], operands[6]);\n- std::swap (operands[1], operands[7]);\n- std::swap (operands[2], operands[4]);\n- std::swap (operands[3], operands[5]);\n- }\n-\n if (aarch64_gen_adjusted_ldpstp (operands, true, SImode, SIGN_EXTEND))\n DONE;\n else\n@@ -320,18 +220,6 @@\n \"aarch64_operands_adjust_ok_for_ldpstp (operands, true, SImode)\"\n [(const_int 0)]\n {\n- rtx base, offset_1, offset_2;\n-\n- extract_base_offset_in_addr (operands[1], &base, &offset_1);\n- extract_base_offset_in_addr (operands[3], &base, &offset_2);\n- if (INTVAL (offset_1) > INTVAL (offset_2))\n- {\n- std::swap (operands[0], operands[6]);\n- std::swap (operands[1], operands[7]);\n- std::swap (operands[2], operands[4]);\n- std::swap (operands[3], operands[5]);\n- }\n-\n if (aarch64_gen_adjusted_ldpstp (operands, true, SImode, ZERO_EXTEND))\n DONE;\n else\n@@ -352,18 +240,6 @@\n \"aarch64_operands_adjust_ok_for_ldpstp (operands, false, mode)\"\n [(const_int 0)]\n {\n- rtx base, offset_1, offset_2;\n-\n- extract_base_offset_in_addr (operands[0], &base, &offset_1);\n- extract_base_offset_in_addr (operands[2], &base, &offset_2);\n- if (INTVAL (offset_1) > INTVAL (offset_2))\n- {\n- std::swap (operands[0], operands[6]);\n- std::swap (operands[1], operands[7]);\n- std::swap (operands[2], operands[4]);\n- std::swap (operands[3], operands[5]);\n- }\n-\n if (aarch64_gen_adjusted_ldpstp (operands, false, mode, UNKNOWN))\n DONE;\n else\n@@ -384,18 +260,6 @@\n \"aarch64_operands_adjust_ok_for_ldpstp (operands, false, mode)\"\n [(const_int 0)]\n {\n- rtx base, offset_1, offset_2;\n-\n- extract_base_offset_in_addr (operands[0], &base, &offset_1);\n- extract_base_offset_in_addr (operands[2], &base, &offset_2);\n- if (INTVAL (offset_1) > INTVAL (offset_2))\n- {\n- std::swap (operands[0], operands[6]);\n- std::swap (operands[1], operands[7]);\n- std::swap (operands[2], operands[4]);\n- std::swap (operands[3], operands[5]);\n- }\n-\n if (aarch64_gen_adjusted_ldpstp (operands, false, mode, UNKNOWN))\n DONE;\n else\ndiff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h\nindex ed5d373dc105feec5bff3885cef0f4d7f8c75b52..3ba1cfbf73f0a313ead91a08b83bc582457d952e 100644\n--- a/gcc/config/aarch64/aarch64-protos.h\n+++ b/gcc/config/aarch64/aarch64-protos.h\n@@ -470,6 +470,7 @@ int aarch64_ccmp_mode_to_code (machine_mode mode);\n bool extract_base_offset_in_addr (rtx mem, rtx *base, rtx *offset);\n bool aarch64_operands_ok_for_ldpstp (rtx *, bool, machine_mode);\n bool aarch64_operands_adjust_ok_for_ldpstp (rtx *, bool, scalar_mode);\n+void aarch64_swap_ldrstr_operands (rtx *, bool);\n \n extern void aarch64_asm_output_pool_epilogue (FILE *, const char *,\n \t\t\t\t\t tree, HOST_WIDE_INT);\ndiff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c\nindex dec920f996d7591e180ac844d8fdf1b18a3e7a8d..276e63c733f596a24ee1c5e2411d7a5fb6b88964 100644\n--- a/gcc/config/aarch64/aarch64.c\n+++ b/gcc/config/aarch64/aarch64.c\n@@ -14772,9 +14772,18 @@ aarch64_operands_ok_for_ldpstp (rtx *operands, bool load,\n \n /* In increasing order, the last load can clobber the address. */\n if (offval_1 > offval_2 && reg_mentioned_p (reg_2, mem_2))\n- return false;\n+\treturn false;\n }\n \n+ /* One of the memory accesses must be a mempair operand.\n+ If it is not the first one, they need to be swapped by the\n+ peephole. */\n+ if (!(aarch64_legitimate_address_p (GET_MODE (mem_1),\n+\t\t\t\t XEXP (mem_1, 0), PARALLEL, 0)\n+\t|| aarch64_legitimate_address_p (GET_MODE (mem_2),\n+\t\t\t\t\t XEXP (mem_2, 0), PARALLEL, 0)))\n+ return false;\n+\n if (REG_P (reg_1) && FP_REGNUM_P (REGNO (reg_1)))\n rclass_1 = FP_REGS;\n else\n@@ -14792,6 +14801,40 @@ aarch64_operands_ok_for_ldpstp (rtx *operands, bool load,\n return true;\n }\n \n+/* Given OPERANDS of consecutive load/store that can be merged,\n+ swap them if they are not in ascending order. */\n+void\n+aarch64_swap_ldrstr_operands (rtx* operands, bool load)\n+{\n+ rtx mem_1, mem_2, base_1, base_2, offset_1, offset_2;\n+ HOST_WIDE_INT offval_1, offval_2;\n+\n+ if (load)\n+ {\n+ mem_1 = operands[1];\n+ mem_2 = operands[3];\n+ }\n+ else\n+ {\n+ mem_1 = operands[0];\n+ mem_2 = operands[2];\n+ }\n+\n+ extract_base_offset_in_addr (mem_1, &base_1, &offset_1);\n+ extract_base_offset_in_addr (mem_2, &base_2, &offset_2);\n+\n+ offval_1 = INTVAL (offset_1);\n+ offval_2 = INTVAL (offset_2);\n+\n+ if (offval_1 > offval_2)\n+ {\n+ /* Irrespective of whether this is a load or a store,\n+\t we do the same swap. */\n+ std::swap (operands[0], operands[2]);\n+ std::swap (operands[1], operands[3]);\n+ }\n+}\n+\n /* Given OPERANDS of consecutive load/store, check if we can merge\n them into ldp/stp by adjusting the offset. LOAD is true if they\n are load instructions. MODE is the mode of memory operands.\n@@ -14951,7 +14994,7 @@ bool\n aarch64_gen_adjusted_ldpstp (rtx *operands, bool load,\n \t\t\t scalar_mode mode, RTX_CODE code)\n {\n- rtx base, offset, t1, t2;\n+ rtx base, offset_1, offset_2, t1, t2;\n rtx mem_1, mem_2, mem_3, mem_4;\n HOST_WIDE_INT off_val, abs_off, adj_off, new_off, stp_off_limit, msize;\n \n@@ -14971,13 +15014,24 @@ aarch64_gen_adjusted_ldpstp (rtx *operands, bool load,\n gcc_assert (code == UNKNOWN);\n }\n \n- extract_base_offset_in_addr (mem_1, &base, &offset);\n- gcc_assert (base != NULL_RTX && offset != NULL_RTX);\n+ extract_base_offset_in_addr (mem_1, &base, &offset_1);\n+ extract_base_offset_in_addr (mem_2, &base, &offset_2);\n+ gcc_assert (base != NULL_RTX && offset_1 != NULL_RTX\n+\t && offset_2 != NULL_RTX);\n+\n+ if (INTVAL (offset_1) > INTVAL (offset_2))\n+ {\n+ std::swap (operands[0], operands[6]);\n+ std::swap (operands[1], operands[7]);\n+ std::swap (operands[2], operands[4]);\n+ std::swap (operands[3], operands[5]);\n+ }\n+\n \n /* Adjust offset thus it can fit in ldp/stp instruction. */\n msize = GET_MODE_SIZE (mode);\n stp_off_limit = msize * 0x40;\n- off_val = INTVAL (offset);\n+ off_val = INTVAL (offset_1);\n abs_off = (off_val < 0) ? -off_val : off_val;\n new_off = abs_off % stp_off_limit;\n adj_off = abs_off - new_off;\n","prefixes":["AArch64"]}