{"id":812974,"url":"http://patchwork.ozlabs.org/api/patches/812974/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20170912170725.29733-6-marek.vasut+renesas@gmail.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170912170725.29733-6-marek.vasut+renesas@gmail.com>","list_archive_url":null,"date":"2017-09-12T17:07:25","name":"[U-Boot,6/6] usb: Drop the EHCI RCar Gen3","commit_ref":null,"pull_url":null,"state":"accepted","archived":false,"hash":"062b52bf01a3bfaced277f927dbf2b623104a020","submitter":{"id":1124,"url":"http://patchwork.ozlabs.org/api/people/1124/?format=json","name":"Marek Vasut","email":"marek.vasut@gmail.com"},"delegate":{"id":1750,"url":"http://patchwork.ozlabs.org/api/users/1750/?format=json","username":"iwamatsu","first_name":"Nobuhiro","last_name":"Iwamatsu","email":"iwamatsu@nigauri.org"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20170912170725.29733-6-marek.vasut+renesas@gmail.com/mbox/","series":[{"id":2744,"url":"http://patchwork.ozlabs.org/api/series/2744/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=2744","date":"2017-09-12T17:07:21","name":"[U-Boot,1/6] ARM: rmobile: dts: Add EHCI USB nodes to r8a7796","version":1,"mbox":"http://patchwork.ozlabs.org/series/2744/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/812974/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/812974/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"Since we use EHCI generic driver on RCar Gen3 , this driver is useless.\nRemove it.\n\nSigned-off-by: Marek Vasut \nCc: Nobuhiro Iwamatsu \n---\n drivers/usb/host/Kconfig | 8 ---\n drivers/usb/host/Makefile | 1 -\n drivers/usb/host/ehci-rcar_gen3.c | 106 --------------------------------------\n 3 files changed, 115 deletions(-)\n delete mode 100644 drivers/usb/host/ehci-rcar_gen3.c","diff":"diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig\nindex eb035a476b..5438feb8f5 100644\n--- a/drivers/usb/host/Kconfig\n+++ b/drivers/usb/host/Kconfig\n@@ -148,14 +148,6 @@ config USB_EHCI_PCI\n \thelp\n \t Enables support for the PCI-based EHCI controller.\n \n-config USB_EHCI_RCAR_GEN3\n-\tbool \"Support for Renesas RCar M3/H3 EHCI USB controller\"\n-\tdepends on RCAR_GEN3\n-\tdefault y\n-\t---help---\n-\t Enables support for the on-chip EHCI controller on Renesas\n-\t R8A7795 and R8A7796 SoCs.\n-\n config USB_EHCI_ZYNQ\n \tbool \"Support for Xilinx Zynq on-chip EHCI USB controller\"\n \tdepends on ARCH_ZYNQ\ndiff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile\nindex ab5a99faa8..d3ff591a71 100644\n--- a/drivers/usb/host/Makefile\n+++ b/drivers/usb/host/Makefile\n@@ -46,7 +46,6 @@ obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o\n obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o\n obj-$(CONFIG_USB_EHCI_VF) += ehci-vf.o\n obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o\n-obj-$(CONFIG_USB_EHCI_RCAR_GEN3) += ehci-rcar_gen3.o\n obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o\n \n # xhci\ndiff --git a/drivers/usb/host/ehci-rcar_gen3.c b/drivers/usb/host/ehci-rcar_gen3.c\ndeleted file mode 100644\nindex 525e7f3573..0000000000\n--- a/drivers/usb/host/ehci-rcar_gen3.c\n+++ /dev/null\n@@ -1,106 +0,0 @@\n-/*\n- * drivers/usb/host/ehci-rcar_gen3.\n- *\tThis file is EHCI HCD (Host Controller Driver) for USB.\n- *\n- * Copyright (C) 2015-2017 Renesas Electronics Corporation\n- *\n- * SPDX-License-Identifier: GPL-2.0+\n- */\n-\n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \"ehci.h\"\n-\n-#define RCAR_GEN3_USB_BASE(n)\t(0xEE080000 + ((n) * 0x20000))\n-\n-#define EHCI_USBCMD\t\t0x120\n-\n-#define CORE_SPD_RSM_TIMSET\t0x30c\n-#define CORE_OC_TIMSET\t\t0x310\n-\n-/* Register offset */\n-#define AHB_OFFSET\t\t0x200\n-\n-#define BASE_HSUSB\t\t0xE6590000\n-#define REG_LPSTS\t\t(BASE_HSUSB + 0x0102)\t/* 16bit */\n-#define SUSPM\t\t\t0x4000\n-#define SUSPM_NORMAL\t\tBIT(14)\n-#define REG_UGCTRL2\t\t(BASE_HSUSB + 0x0184)\t/* 32bit */\n-#define USB0SEL\t\t\t0x00000030\n-#define USB0SEL_EHCI\t\t0x00000010\n-\n-#define SMSTPCR7\t\t0xE615014C\n-#define SMSTPCR700\t\tBIT(0)\t/* EHCI3 */\n-#define SMSTPCR701\t\tBIT(1)\t/* EHCI2 */\n-#define SMSTPCR702\t\tBIT(2)\t/* EHCI1 */\n-#define SMSTPCR703\t\tBIT(3)\t/* EHCI0 */\n-#define SMSTPCR704\t\tBIT(4)\t/* HSUSB */\n-\n-#define AHB_PLL_RST\t\tBIT(1)\n-\n-#define USBH_INTBEN\t\tBIT(2)\n-#define USBH_INTAEN\t\tBIT(1)\n-\n-#define AHB_INT_ENABLE\t\t0x200\n-#define AHB_USBCTR\t\t0x20c\n-\n-int ehci_hcd_stop(int index)\n-{\n-#if defined(CONFIG_R8A7795)\n-\tconst u32 mask = SMSTPCR703 | SMSTPCR702 | SMSTPCR701 | SMSTPCR700;\n-#else\n-\tconst u32 mask = SMSTPCR703 | SMSTPCR702;\n-#endif\n-\tconst u32 base = RCAR_GEN3_USB_BASE(index);\n-\tint ret;\n-\n-\t/* Reset EHCI */\n-\tsetbits_le32((uintptr_t)(base + EHCI_USBCMD), CMD_RESET);\n-\tret = wait_for_bit(\"ehci-rcar\", (void *)(uintptr_t)base + EHCI_USBCMD,\n-\t\t\t CMD_RESET, false, 10, true);\n-\tif (ret) {\n-\t\tprintf(\"ehci-rcar: reset failed (index=%i, ret=%i).\\n\",\n-\t\t index, ret);\n-\t}\n-\n-\tsetbits_le32(SMSTPCR7, BIT(3 - index));\n-\n-\tif ((readl(SMSTPCR7) & mask) == mask)\n-\t\tsetbits_le32(SMSTPCR7, SMSTPCR704);\n-\n-\treturn 0;\n-}\n-\n-int ehci_hcd_init(int index, enum usb_init_type init,\n-\t\t struct ehci_hccr **hccr, struct ehci_hcor **hcor)\n-{\n-\tconst void __iomem *base =\n-\t\t(void __iomem *)(uintptr_t)RCAR_GEN3_USB_BASE(index);\n-\tstruct usb_ehci *ehci = (struct usb_ehci *)(uintptr_t)base;\n-\n-\tclrbits_le32(SMSTPCR7, BIT(3 - index));\n-\tclrbits_le32(SMSTPCR7, SMSTPCR704);\n-\n-\t*hccr = (struct ehci_hccr *)((uintptr_t)&ehci->caplength);\n-\t*hcor = (struct ehci_hcor *)((uintptr_t)*hccr +\n-\t\t\tHC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));\n-\n-\t/* Enable interrupt */\n-\tsetbits_le32(base + AHB_INT_ENABLE, USBH_INTBEN | USBH_INTAEN);\n-\twritel(0x014e029b, base + CORE_SPD_RSM_TIMSET);\n-\twritel(0x000209ab, base + CORE_OC_TIMSET);\n-\n-\t/* Choice USB0SEL */\n-\tclrsetbits_le32(REG_UGCTRL2, USB0SEL, USB0SEL_EHCI);\n-\n-\t/* Clock & Reset */\n-\tclrbits_le32(base + AHB_USBCTR, AHB_PLL_RST);\n-\n-\t/* low power status */\n-\tclrsetbits_le16(REG_LPSTS, SUSPM, SUSPM_NORMAL);\n-\n-\treturn 0;\n-}\n","prefixes":["U-Boot","6/6"]}