{"id":812951,"url":"http://patchwork.ozlabs.org/api/patches/812951/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170912162513.21694-5-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170912162513.21694-5-richard.henderson@linaro.org>","list_archive_url":null,"date":"2017-09-12T16:25:01","name":"[v2,04/16] tcg: Add tcg_op_supported","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"56448678046f56928eac9877984a114d0017a3f1","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170912162513.21694-5-richard.henderson@linaro.org/mbox/","series":[{"id":2737,"url":"http://patchwork.ozlabs.org/api/series/2737/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2737","date":"2017-09-12T16:24:59","name":"TCG vectorization and example conversion","version":2,"mbox":"http://patchwork.ozlabs.org/series/2737/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/812951/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/812951/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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-0700","Message-Id":"<20170912162513.21694-5-richard.henderson@linaro.org>","X-Mailer":"git-send-email 2.13.5","In-Reply-To":"<20170912162513.21694-1-richard.henderson@linaro.org>","References":"<20170912162513.21694-1-richard.henderson@linaro.org>","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"8bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400e:c05::234","Subject":"[Qemu-devel] [PATCH v2 04/16] tcg: Add tcg_op_supported","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"alex.bennee@linaro.org, f4bug@amsat.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"Reviewed-by: Philippe Mathieu-Daudé \nReviewed-by: Alex Bennée \nSigned-off-by: Richard Henderson \n---\n tcg/tcg.h | 2 +\n tcg/tcg.c | 310 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\n 2 files changed, 312 insertions(+)","diff":"diff --git a/tcg/tcg.h b/tcg/tcg.h\nindex 69b1fdf457..b81c67a754 100644\n--- a/tcg/tcg.h\n+++ b/tcg/tcg.h\n@@ -961,6 +961,8 @@ do {\\\n #define tcg_temp_free_ptr(T) tcg_temp_free_i64(TCGV_PTR_TO_NAT(T))\n #endif\n \n+bool tcg_op_supported(TCGOpcode op);\n+\n void tcg_gen_callN(TCGContext *s, void *func,\n TCGArg ret, int nargs, TCGArg *args);\n \ndiff --git a/tcg/tcg.c b/tcg/tcg.c\nindex bc65d01618..9aea00d9b4 100644\n--- a/tcg/tcg.c\n+++ b/tcg/tcg.c\n@@ -749,6 +749,316 @@ int tcg_check_temp_count(void)\n }\n #endif\n \n+/* Return true if OP may appear in the opcode stream.\n+ Test the runtime variable that controls each opcode. */\n+bool tcg_op_supported(TCGOpcode op)\n+{\n+ switch (op) {\n+ case INDEX_op_discard:\n+ case INDEX_op_set_label:\n+ case INDEX_op_call:\n+ case INDEX_op_br:\n+ case INDEX_op_mb:\n+ case INDEX_op_insn_start:\n+ case INDEX_op_exit_tb:\n+ case INDEX_op_goto_tb:\n+ case INDEX_op_qemu_ld_i32:\n+ case INDEX_op_qemu_st_i32:\n+ case INDEX_op_qemu_ld_i64:\n+ case INDEX_op_qemu_st_i64:\n+ return true;\n+\n+ case INDEX_op_goto_ptr:\n+ return TCG_TARGET_HAS_goto_ptr;\n+\n+ case INDEX_op_mov_i32:\n+ case INDEX_op_movi_i32:\n+ case INDEX_op_setcond_i32:\n+ case INDEX_op_brcond_i32:\n+ case INDEX_op_ld8u_i32:\n+ case INDEX_op_ld8s_i32:\n+ case INDEX_op_ld16u_i32:\n+ case INDEX_op_ld16s_i32:\n+ case INDEX_op_ld_i32:\n+ case INDEX_op_st8_i32:\n+ case INDEX_op_st16_i32:\n+ case INDEX_op_st_i32:\n+ case INDEX_op_add_i32:\n+ case INDEX_op_sub_i32:\n+ case INDEX_op_mul_i32:\n+ case INDEX_op_and_i32:\n+ case INDEX_op_or_i32:\n+ case INDEX_op_xor_i32:\n+ case INDEX_op_shl_i32:\n+ case INDEX_op_shr_i32:\n+ case INDEX_op_sar_i32:\n+ return true;\n+\n+ case INDEX_op_movcond_i32:\n+ return TCG_TARGET_HAS_movcond_i32;\n+ case INDEX_op_div_i32:\n+ case INDEX_op_divu_i32:\n+ return TCG_TARGET_HAS_div_i32;\n+ case INDEX_op_rem_i32:\n+ case INDEX_op_remu_i32:\n+ return TCG_TARGET_HAS_rem_i32;\n+ case INDEX_op_div2_i32:\n+ case INDEX_op_divu2_i32:\n+ return TCG_TARGET_HAS_div2_i32;\n+ case INDEX_op_rotl_i32:\n+ case INDEX_op_rotr_i32:\n+ return TCG_TARGET_HAS_rot_i32;\n+ case INDEX_op_deposit_i32:\n+ return TCG_TARGET_HAS_deposit_i32;\n+ case INDEX_op_extract_i32:\n+ return TCG_TARGET_HAS_extract_i32;\n+ case INDEX_op_sextract_i32:\n+ return TCG_TARGET_HAS_sextract_i32;\n+ case INDEX_op_add2_i32:\n+ return TCG_TARGET_HAS_add2_i32;\n+ case INDEX_op_sub2_i32:\n+ return TCG_TARGET_HAS_sub2_i32;\n+ case INDEX_op_mulu2_i32:\n+ return TCG_TARGET_HAS_mulu2_i32;\n+ case INDEX_op_muls2_i32:\n+ return TCG_TARGET_HAS_muls2_i32;\n+ case INDEX_op_muluh_i32:\n+ return TCG_TARGET_HAS_muluh_i32;\n+ case INDEX_op_mulsh_i32:\n+ return TCG_TARGET_HAS_mulsh_i32;\n+ case INDEX_op_ext8s_i32:\n+ return TCG_TARGET_HAS_ext8s_i32;\n+ case INDEX_op_ext16s_i32:\n+ return TCG_TARGET_HAS_ext16s_i32;\n+ case INDEX_op_ext8u_i32:\n+ return TCG_TARGET_HAS_ext8u_i32;\n+ case INDEX_op_ext16u_i32:\n+ return TCG_TARGET_HAS_ext16u_i32;\n+ case INDEX_op_bswap16_i32:\n+ return TCG_TARGET_HAS_bswap16_i32;\n+ case INDEX_op_bswap32_i32:\n+ return TCG_TARGET_HAS_bswap32_i32;\n+ case INDEX_op_not_i32:\n+ return TCG_TARGET_HAS_not_i32;\n+ case INDEX_op_neg_i32:\n+ return TCG_TARGET_HAS_neg_i32;\n+ case INDEX_op_andc_i32:\n+ return TCG_TARGET_HAS_andc_i32;\n+ case INDEX_op_orc_i32:\n+ return TCG_TARGET_HAS_orc_i32;\n+ case INDEX_op_eqv_i32:\n+ return TCG_TARGET_HAS_eqv_i32;\n+ case INDEX_op_nand_i32:\n+ return TCG_TARGET_HAS_nand_i32;\n+ case INDEX_op_nor_i32:\n+ return TCG_TARGET_HAS_nor_i32;\n+ case INDEX_op_clz_i32:\n+ return TCG_TARGET_HAS_clz_i32;\n+ case INDEX_op_ctz_i32:\n+ return TCG_TARGET_HAS_ctz_i32;\n+ case INDEX_op_ctpop_i32:\n+ return TCG_TARGET_HAS_ctpop_i32;\n+\n+ case INDEX_op_brcond2_i32:\n+ case INDEX_op_setcond2_i32:\n+ return TCG_TARGET_REG_BITS == 32;\n+\n+ case INDEX_op_mov_i64:\n+ case INDEX_op_movi_i64:\n+ case INDEX_op_setcond_i64:\n+ case INDEX_op_brcond_i64:\n+ case INDEX_op_ld8u_i64:\n+ case INDEX_op_ld8s_i64:\n+ case INDEX_op_ld16u_i64:\n+ case INDEX_op_ld16s_i64:\n+ case INDEX_op_ld32u_i64:\n+ case INDEX_op_ld32s_i64:\n+ case INDEX_op_ld_i64:\n+ case INDEX_op_st8_i64:\n+ case INDEX_op_st16_i64:\n+ case INDEX_op_st32_i64:\n+ case INDEX_op_st_i64:\n+ case INDEX_op_add_i64:\n+ case INDEX_op_sub_i64:\n+ case INDEX_op_mul_i64:\n+ case INDEX_op_and_i64:\n+ case INDEX_op_or_i64:\n+ case INDEX_op_xor_i64:\n+ case INDEX_op_shl_i64:\n+ case INDEX_op_shr_i64:\n+ case INDEX_op_sar_i64:\n+ case INDEX_op_ext_i32_i64:\n+ case INDEX_op_extu_i32_i64:\n+ return TCG_TARGET_REG_BITS == 64;\n+\n+ case INDEX_op_movcond_i64:\n+ return TCG_TARGET_HAS_movcond_i64;\n+ case INDEX_op_div_i64:\n+ case INDEX_op_divu_i64:\n+ return TCG_TARGET_HAS_div_i64;\n+ case INDEX_op_rem_i64:\n+ case INDEX_op_remu_i64:\n+ return TCG_TARGET_HAS_rem_i64;\n+ case INDEX_op_div2_i64:\n+ case INDEX_op_divu2_i64:\n+ return TCG_TARGET_HAS_div2_i64;\n+ case INDEX_op_rotl_i64:\n+ case INDEX_op_rotr_i64:\n+ return TCG_TARGET_HAS_rot_i64;\n+ case INDEX_op_deposit_i64:\n+ return TCG_TARGET_HAS_deposit_i64;\n+ case INDEX_op_extract_i64:\n+ return TCG_TARGET_HAS_extract_i64;\n+ case INDEX_op_sextract_i64:\n+ return TCG_TARGET_HAS_sextract_i64;\n+ case INDEX_op_extrl_i64_i32:\n+ return TCG_TARGET_HAS_extrl_i64_i32;\n+ case INDEX_op_extrh_i64_i32:\n+ return TCG_TARGET_HAS_extrh_i64_i32;\n+ case INDEX_op_ext8s_i64:\n+ return TCG_TARGET_HAS_ext8s_i64;\n+ case INDEX_op_ext16s_i64:\n+ return TCG_TARGET_HAS_ext16s_i64;\n+ case INDEX_op_ext32s_i64:\n+ return TCG_TARGET_HAS_ext32s_i64;\n+ case INDEX_op_ext8u_i64:\n+ return TCG_TARGET_HAS_ext8u_i64;\n+ case INDEX_op_ext16u_i64:\n+ return TCG_TARGET_HAS_ext16u_i64;\n+ case INDEX_op_ext32u_i64:\n+ return TCG_TARGET_HAS_ext32u_i64;\n+ case INDEX_op_bswap16_i64:\n+ return TCG_TARGET_HAS_bswap16_i64;\n+ case INDEX_op_bswap32_i64:\n+ return TCG_TARGET_HAS_bswap32_i64;\n+ case INDEX_op_bswap64_i64:\n+ return TCG_TARGET_HAS_bswap64_i64;\n+ case INDEX_op_not_i64:\n+ return TCG_TARGET_HAS_not_i64;\n+ case INDEX_op_neg_i64:\n+ return TCG_TARGET_HAS_neg_i64;\n+ case INDEX_op_andc_i64:\n+ return TCG_TARGET_HAS_andc_i64;\n+ case INDEX_op_orc_i64:\n+ return TCG_TARGET_HAS_orc_i64;\n+ case INDEX_op_eqv_i64:\n+ return TCG_TARGET_HAS_eqv_i64;\n+ case INDEX_op_nand_i64:\n+ return TCG_TARGET_HAS_nand_i64;\n+ case INDEX_op_nor_i64:\n+ return TCG_TARGET_HAS_nor_i64;\n+ case INDEX_op_clz_i64:\n+ return TCG_TARGET_HAS_clz_i64;\n+ case INDEX_op_ctz_i64:\n+ return TCG_TARGET_HAS_ctz_i64;\n+ case INDEX_op_ctpop_i64:\n+ return TCG_TARGET_HAS_ctpop_i64;\n+ case INDEX_op_add2_i64:\n+ return TCG_TARGET_HAS_add2_i64;\n+ case INDEX_op_sub2_i64:\n+ return TCG_TARGET_HAS_sub2_i64;\n+ case INDEX_op_mulu2_i64:\n+ return TCG_TARGET_HAS_mulu2_i64;\n+ case INDEX_op_muls2_i64:\n+ return TCG_TARGET_HAS_muls2_i64;\n+ case INDEX_op_muluh_i64:\n+ return TCG_TARGET_HAS_muluh_i64;\n+ case INDEX_op_mulsh_i64:\n+ return TCG_TARGET_HAS_mulsh_i64;\n+\n+ case INDEX_op_mov_v64:\n+ case INDEX_op_movi_v64:\n+ case INDEX_op_ld_v64:\n+ case INDEX_op_st_v64:\n+ case INDEX_op_and_v64:\n+ case INDEX_op_or_v64:\n+ case INDEX_op_xor_v64:\n+ case INDEX_op_add8_v64:\n+ case INDEX_op_add16_v64:\n+ case INDEX_op_add32_v64:\n+ case INDEX_op_sub8_v64:\n+ case INDEX_op_sub16_v64:\n+ case INDEX_op_sub32_v64:\n+ return TCG_TARGET_HAS_v64;\n+\n+ case INDEX_op_mov_v128:\n+ case INDEX_op_movi_v128:\n+ case INDEX_op_ld_v128:\n+ case INDEX_op_st_v128:\n+ case INDEX_op_and_v128:\n+ case INDEX_op_or_v128:\n+ case INDEX_op_xor_v128:\n+ case INDEX_op_add8_v128:\n+ case INDEX_op_add16_v128:\n+ case INDEX_op_add32_v128:\n+ case INDEX_op_add64_v128:\n+ case INDEX_op_sub8_v128:\n+ case INDEX_op_sub16_v128:\n+ case INDEX_op_sub32_v128:\n+ case INDEX_op_sub64_v128:\n+ return TCG_TARGET_HAS_v128;\n+\n+ case INDEX_op_mov_v256:\n+ case INDEX_op_movi_v256:\n+ case INDEX_op_ld_v256:\n+ case INDEX_op_st_v256:\n+ case INDEX_op_and_v256:\n+ case INDEX_op_or_v256:\n+ case INDEX_op_xor_v256:\n+ case INDEX_op_add8_v256:\n+ case INDEX_op_add16_v256:\n+ case INDEX_op_add32_v256:\n+ case INDEX_op_add64_v256:\n+ case INDEX_op_sub8_v256:\n+ case INDEX_op_sub16_v256:\n+ case INDEX_op_sub32_v256:\n+ case INDEX_op_sub64_v256:\n+ return TCG_TARGET_HAS_v256;\n+\n+ case INDEX_op_not_v64:\n+ return TCG_TARGET_HAS_not_v64;\n+ case INDEX_op_not_v128:\n+ return TCG_TARGET_HAS_not_v128;\n+ case INDEX_op_not_v256:\n+ return TCG_TARGET_HAS_not_v256;\n+\n+ case INDEX_op_andc_v64:\n+ return TCG_TARGET_HAS_andc_v64;\n+ case INDEX_op_andc_v128:\n+ return TCG_TARGET_HAS_andc_v128;\n+ case INDEX_op_andc_v256:\n+ return TCG_TARGET_HAS_andc_v256;\n+\n+ case INDEX_op_orc_v64:\n+ return TCG_TARGET_HAS_orc_v64;\n+ case INDEX_op_orc_v128:\n+ return TCG_TARGET_HAS_orc_v128;\n+ case INDEX_op_orc_v256:\n+ return TCG_TARGET_HAS_orc_v256;\n+\n+ case INDEX_op_neg8_v64:\n+ case INDEX_op_neg16_v64:\n+ case INDEX_op_neg32_v64:\n+ return TCG_TARGET_HAS_neg_v64;\n+\n+ case INDEX_op_neg8_v128:\n+ case INDEX_op_neg16_v128:\n+ case INDEX_op_neg32_v128:\n+ case INDEX_op_neg64_v128:\n+ return TCG_TARGET_HAS_neg_v128;\n+\n+ case INDEX_op_neg8_v256:\n+ case INDEX_op_neg16_v256:\n+ case INDEX_op_neg32_v256:\n+ case INDEX_op_neg64_v256:\n+ return TCG_TARGET_HAS_neg_v256;\n+\n+ case NB_OPS:\n+ break;\n+ }\n+ g_assert_not_reached();\n+}\n+\n /* Note: we convert the 64 bit args to 32 bit and do some alignment\n and endian swap. Maybe it would be better to do the alignment\n and endian swap in tcg_reg_alloc_call(). */\n","prefixes":["v2","04/16"]}