{"id":812741,"url":"http://patchwork.ozlabs.org/api/patches/812741/?format=json","web_url":"http://patchwork.ozlabs.org/project/devicetree-bindings/patch/1505207272-16983-2-git-send-email-chaotian.jing@mediatek.com/","project":{"id":37,"url":"http://patchwork.ozlabs.org/api/projects/37/?format=json","name":"Devicetree Bindings","link_name":"devicetree-bindings","list_id":"devicetree.vger.kernel.org","list_email":"devicetree@vger.kernel.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1505207272-16983-2-git-send-email-chaotian.jing@mediatek.com>","list_archive_url":null,"date":"2017-09-12T09:07:41","name":"[01/12] mmc: dt-bindings: update Mediatek MMC bindings","commit_ref":null,"pull_url":null,"state":"changes-requested","archived":true,"hash":"ef5f688d1a06be7d157abc11a843caae7d6dc3a6","submitter":{"id":67412,"url":"http://patchwork.ozlabs.org/api/people/67412/?format=json","name":"Chaotian Jing (井朝天)","email":"chaotian.jing@mediatek.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/devicetree-bindings/patch/1505207272-16983-2-git-send-email-chaotian.jing@mediatek.com/mbox/","series":[{"id":2643,"url":"http://patchwork.ozlabs.org/api/series/2643/?format=json","web_url":"http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=2643","date":"2017-09-12T09:07:41","name":"[01/12] mmc: dt-bindings: update Mediatek MMC bindings","version":1,"mbox":"http://patchwork.ozlabs.org/series/2643/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/812741/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/812741/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xrzbB3NXYz9s81\n\tfor ;\n\tTue, 12 Sep 2017 19:12:38 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751393AbdILJIH (ORCPT\n\t);\n\tTue, 12 Sep 2017 05:08:07 -0400","from mailgw02.mediatek.com ([210.61.82.184]:62595 \"EHLO\n\tmailgw02.mediatek.com\" rhost-flags-OK-FAIL-OK-FAIL) by\n\tvger.kernel.org with ESMTP id S1751311AbdILJIF (ORCPT\n\t); Tue, 12 Sep 2017 05:08:05 -0400","from mtkexhb02.mediatek.inc [(172.21.101.103)] by\n\tmailgw02.mediatek.com (envelope-from )\n\t(mhqrelay.mediatek.com ESMTP with TLS)\n\twith ESMTP id 1564298600; Tue, 12 Sep 2017 17:08:01 +0800","from mtkcas08.mediatek.inc (172.21.101.126) by\n\tmtkmbs03n2.mediatek.inc (172.21.101.182) with Microsoft SMTP Server\n\t(TLS) id 15.0.1210.3; Tue, 12 Sep 2017 17:08:00 +0800","from localhost.localdomain (10.17.3.153) by mtkcas08.mediatek.inc\n\t(172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via\n\tFrontend Transport; Tue, 12 Sep 2017 17:07:58 +0800"],"X-UUID":"9ef57d157b34431dac53b231046f242b-20170912","From":"Chaotian Jing ","To":"Ulf Hansson ","CC":"Rob Herring , Mark Rutland ,\n\tMatthias Brugger ,\n\tCatalin Marinas ,\n\tWill Deacon ,\n\tChaotian Jing ,\n\tyong mao ,\n\tLinus Walleij , \n\tJavier Martinez Canillas ,\n\tHeiner Kallweit ,\n\tPhong LE , ,\n\t, , \n\t,\n\t, ","Subject":"[PATCH 01/12] mmc: dt-bindings: update Mediatek MMC bindings","Date":"Tue, 12 Sep 2017 17:07:41 +0800","Message-ID":"<1505207272-16983-2-git-send-email-chaotian.jing@mediatek.com>","X-Mailer":"git-send-email 1.8.1.1.dirty","In-Reply-To":"<1505207272-16983-1-git-send-email-chaotian.jing@mediatek.com>","References":"<1505207272-16983-1-git-send-email-chaotian.jing@mediatek.com>","MIME-Version":"1.0","Content-Type":"text/plain","X-MTK":"N","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"},"content":"Change the comptiable for support of multi-platform\nAdd description for reg\nAdd description for source_cg\nAdd description for mediatek,latch-ck\n\nSigned-off-by: Chaotian Jing \n---\n Documentation/devicetree/bindings/mmc/mtk-sd.txt | 13 ++++++++++---\n 1 file changed, 10 insertions(+), 3 deletions(-)","diff":"diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.txt b/Documentation/devicetree/bindings/mmc/mtk-sd.txt\nindex 4182ea3..405cd06 100644\n--- a/Documentation/devicetree/bindings/mmc/mtk-sd.txt\n+++ b/Documentation/devicetree/bindings/mmc/mtk-sd.txt\n@@ -7,10 +7,15 @@ This file documents differences between the core properties in mmc.txt\n and the properties used by the msdc driver.\n \n Required properties:\n-- compatible: Should be \"mediatek,mt8173-mmc\",\"mediatek,mt8135-mmc\"\n+- compatible: value should be either of the following.\n+\t\"mediatek,mt8135-mmc\": for mmc host ip compatible with mt8135\n+\t\"mediatek,mt8173-mmc\": for mmc host ip compatible with mt8173\n+\t\"mediatek,mt2701-mmc\": for mmc host ip compatible with mt2701\n+\t\"mediatek,mt2712-mmc\": for mmc host ip compatible with mt2712\n+- reg: physical base address of the controller and length\n - interrupts: Should contain MSDC interrupt number\n-- clocks: MSDC source clock, HCLK\n-- clock-names: \"source\", \"hclk\"\n+- clocks: MSDC source clock, HCLK, source_cg\n+- clock-names: \"source\", \"hclk\", \"source_cg\"\n - pinctrl-names: should be \"default\", \"state_uhs\"\n - pinctrl-0: should contain default/high speed pin ctrl\n - pinctrl-1: should contain uhs mode pin ctrl\n@@ -30,6 +35,8 @@ Optional properties:\n - mediatek,hs400-cmd-resp-sel-rising: HS400 command response sample selection\n \t\t\t\t If present,HS400 command responses are sampled on rising edges.\n \t\t\t\t If not present,HS400 command responses are sampled on falling edges.\n+- mediatek,latch-ck: Some projects do not support enhance_rx, need set correct latch-ck to avoid data crc\n+\t\t error caused by stop clock(fifo full)\n \n Examples:\n mmc0: mmc@11230000 {\n","prefixes":["01/12"]}